Re: [PATCH] PCI: qcom: Program correct T_POWER_ON value for L1.2 exit timing

[Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>]

On 11/4/2025 5:59 PM, Konrad Dybcio wrote:
> On 11/4/25 1:12 PM, Krishna Chaitanya Chundru wrote:
>> The T_POWER_ON indicates the time (in μs) that a Port requires the port
>> on the opposite side of Link to wait in L1.2.Exit after sampling CLKREQ#
>> asserted before actively driving the interface. This value is used by
>> the ASPM driver to compute the LTR_L1.2_THRESHOLD.
>>
>> Currently, the root port exposes a T_POWER_ON value of zero in the L1SS
>> capability registers, leading to incorrect LTR_L1.2_THRESHOLD calculations.
>> This can result in improper L1.2 exit behavior and can trigger AER's.
>>
>> To address this, program the T_POWER_ON value to 80us (scale = 1,
>> value = 8) in the PCI_L1SS_CAP register during host initialization. This
>> ensures that ASPM can take the root port's T_POWER_ON value into account
>> while calculating the LTR_L1.2_THRESHOLD value.
> Is 80us a meaningful value, or "just happens to work"?

This value is given by hardware team.

- Krishna Chaitanya.

>
> Konrad
>