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b=P77ynB6Q7NSd6UKLS/zcNYB0zXvQN7b3MVpyazxPI99OTN+BoLes5XQ8eiwvljxfqH/Rg5NaIkCvAasx4pxhtS7Ia+3ziGDuZBlUAJbMTAbs9o+KCj5KFmlK995FJpyqQJKs+fDNhpH5Zyix9MlNvVKDyjrR3DL4MQ9Nj8mlNi4= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DS0PR12MB6390.namprd12.prod.outlook.com (2603:10b6:8:ce::7) by IA1PR12MB6305.namprd12.prod.outlook.com (2603:10b6:208:3e7::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8335.18; Tue, 14 Jan 2025 15:24:56 +0000 Received: from DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f]) by DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f%4]) with mapi id 15.20.8335.017; Tue, 14 Jan 2025 15:24:56 +0000 Message-ID: <2e88ac60-b99e-46f0-b021-d88192ad891f@amd.com> Date: Tue, 14 Jan 2025 09:24:52 -0600 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 09/16] cxl/pci: Map CXL PCIe Upstream Switch Port RAS registers To: Jonathan Cameron Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, nifan.cxl@gmail.com, dave@stgolabs.net, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, mahesh@linux.ibm.com, ira.weiny@intel.com, oohall@gmail.com, Benjamin.Cheatham@amd.com, rrichter@amd.com, nathan.fontenot@amd.com, Smita.KoralahalliChannabasappa@amd.com, lukas@wunner.de, ming.li@zohomail.com, PradeepVineshReddy.Kodamati@amd.com, alucerop@amd.com References: <20250107143852.3692571-1-terry.bowman@amd.com> <20250107143852.3692571-10-terry.bowman@amd.com> <20250114113540.00006247@huawei.com> Content-Language: en-US From: "Bowman, Terry" In-Reply-To: <20250114113540.00006247@huawei.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?R1VySFQxb0JvbjMzdkV3M1Q4aDBrQUJHYnlFVTFOZXViUXQzSG5xYnhBTmVI?= =?utf-8?B?b1NhcjhaVUpudVhhYWRjRHhDWnZkQVk4ZU5KYkdrVmJXYWs5NDhvTGJHeUdW?= =?utf-8?B?dld3M3AxN2d3YVJZNldkdUdPYWgwR3puOW5qL2M1dW1XK3FvQnhoSkN3dzRQ?= =?utf-8?B?UzVjMTlUYkV6cWw4MWtBZmg0bDR5MDRvVzh0d2RSSFZQTTJGYm84UG9Gd2FU?= =?utf-8?B?YllXL0hHV1dPejk0VGI2Z3gzOExmcG5pTkd3anJIUU94NEJsZFFTMERmSlY3?= =?utf-8?B?dGJjWmpZc29jd3NWNmRGRnYwUThZR0VmMUpiT0s2TGtrd2E1N2IxMmREb05k?= =?utf-8?B?K1luSlF6dzVkclJwNENtdUtVYjVQc0VjWnZYNnlKeGF3TWl5REZTV2hIdXFP?= =?utf-8?B?RFJycXFaREFpNWVUQzBGM0VRT1NkRVArTU44SE05bmtVZ1Z0ZFY5bUkvdStr?= =?utf-8?B?YVF5R20vaU00WldQL1ZLcFlISnVySmNZK2dqaVMvbVpvUk1MejQvMW96L0d0?= =?utf-8?B?RkRVUzZQZHVBeGwzT0VVRTY5cVI1UXh3QlMwSC9NOGU4RGExL0dzbGpYbUkv?= =?utf-8?B?UGt2YUk4WUpQL2lvSGR2cTRGVnZYRldpM3lucVkraWdXejNnV1pPWXI0b0t5?= =?utf-8?B?a2RtQW5wQ040WFA5SURWaUcvSWQ5YkVrUVVmWkdnUFBGR053UUlXNzByS01M?= =?utf-8?B?RmdudXZFcVlBWklPSEF1L2lwbWxIWEJ4V1dYemU0dUw2enRqUWZ5cml2SDEy?= =?utf-8?B?Ukc0Z1VmM2xaV1FjSnI0M0w5eWdUUkMzTmtUZFBKcFlVc1JtREhpSXYvdVhi?= =?utf-8?B?dm9sdERBeE10YllBZGhzTEs1Skc0SU5ldEphMDZiL2ZyOFBHc2NtZE4ydVVz?= =?utf-8?B?L1prdE9HTjlxNWdaNnR2aEhmTXVBUDZ1YVprWk1TcDhkMTcvZktwdHZTWTgy?= =?utf-8?B?T2ZuMGJ6eFNUUVZLMXlMRnlnQXlHVXJnKytQeVVkU1dZbWYxdmV5b2h2UUlt?= =?utf-8?B?TSsxdjFMc1JKeHgycHkrbFRpb3o0TjNVTUdNK0N4Mk14YnNnOWkvMEFpOE1H?= =?utf-8?B?T2pzZlFSSU1OVmxoNkRlZG83VThIc3VFOEZkNllOUDQ2YUVoZHdHdGY5cStI?= =?utf-8?B?SVdzZmxMRHBNb2JLUGFrTG9zUkF6dXpIM2FKSXp4VktqY0xsRncvZFp1Q0V6?= =?utf-8?B?NmhlNWNNZ091bXBrR2lqenlHWW0vN0JRYWFBT20wRXVsTENLRUtQczJ2VnNF?= =?utf-8?B?S0NIb05qSnQ0amhKakhLbitBUkl2d0JhMDh4SUh4RlVPNUROeWJncTdINmY0?= =?utf-8?B?elE3Z0d3Vkk3QjdTMUk3NmJhSExWVjh5NFhSWkM0eGRDVE90R3FaOFUrU2lO?= =?utf-8?B?dE9IODkvVVZZRm5TK3BCQU00cUZHa3lPZmt6anNrM0R5K2pwanJTd2hCaklF?= =?utf-8?B?RTVRbG1Ycjk1bkdkWGE1QWpJbWkwUWUxWUFjNUZzOGlmY0RMcFdSd3RJMk1P?= =?utf-8?B?dmVSTGI2RWdKQkJGQlpqUXp0eDFQbGNieWVWQ1RNaWQyZlFUYjFrMG9FZDAr?= =?utf-8?B?N3VrZVVJVjN4bXZYT2tPQkF0MC9CbmtuNGhWZ1hMd0ZPOUxuWTZ1aGJaRm5B?= =?utf-8?B?V1V6OXdqMFpwT0UxZVIveDQxQ1FOWEZaM3lCRXk4Z3VnSVFDeEVKbERRMFpJ?= =?utf-8?B?aWd1K0lKQThVM1UzTzU0ZWN2QTZzaHBhVjNFZFczdmFuenVQOFpNbTEzV2Nm?= =?utf-8?B?dVdhY3JyNUYxR0l5dDNFZkFPSWFLUzhESGlTTEZNN29nVXI1d2NOTGhVM29D?= =?utf-8?B?N3hjK1VXMk40N2ZySE84SWdjVjVYZ0w3L3RXQWtMdTVTWHFod1RSVjB4Q1Ju?= =?utf-8?B?WmQ1WUxlNENqRlNnOFdzTkhVU2hvMVBEYVJaWnlXaUpoYnhUY0dKaEZkOHNq?= =?utf-8?B?MmdSN2hzcXhuK2Y4dEp2VmlQaCtRc1FFamFBSEM3cVRzS2R0NzlVVlE0MHhM?= =?utf-8?B?SXBOVUVMMzZzc3lJcmZHb2tnSE1qR2EwekpvWGRrc1Z5YkhOeHlqV0VQa0tO?= =?utf-8?B?eEozQTNrSEJUZ1liSTBBQUdJb1lzQTl4Ly9XNHBsSEhhN0xyZW05akpFYVNE?= =?utf-8?Q?ihlsnUk9VieVYqk4/S1w+Oo8l?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 485eb4e8-af1a-42e9-f515-08dd34af99b6 X-MS-Exchange-CrossTenant-AuthSource: DS0PR12MB6390.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2025 15:24:56.1490 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8IxUKQO/VFNx8/XRWkls0p9BbLrbUjDRyxAawMCdgqob5ZFwVkfTbm6RQkZLkyz3ZxsTGCfd3q4bG2QOSyig1w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6305 On 1/14/2025 5:35 AM, Jonathan Cameron wrote: > On Tue, 7 Jan 2025 08:38:45 -0600 > Terry Bowman wrote: > >> Add logic to map CXL PCIe Upstream Switch Port (USP) RAS registers. >> >> Introduce 'struct cxl_regs' member into 'struct cxl_port' to cache a >> pointer to the CXL Upstream Port's mapped RAS registers. >> >> Also, introduce cxl_uport_init_ras_reporting() to perform the USP RAS >> register mapping. This is similar to the existing >> cxl_dport_init_ras_reporting() but for USP devices. >> >> The USP may have multiple downstream endpoints. Before mapping AER >> registers check if the registers are already mapped. >> >> Signed-off-by: Terry Bowman >> --- >> drivers/cxl/core/pci.c | 15 +++++++++++++++ >> drivers/cxl/cxl.h | 4 ++++ >> drivers/cxl/mem.c | 8 ++++++++ >> 3 files changed, 27 insertions(+) >> >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c >> index 1af2d0a14f5d..97e6a15bea88 100644 >> --- a/drivers/cxl/core/pci.c >> +++ b/drivers/cxl/core/pci.c >> @@ -773,6 +773,21 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport) >> writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); >> } >> >> +void cxl_uport_init_ras_reporting(struct cxl_port *port) >> +{ >> + /* uport may have more than 1 downstream EP. Check if already mapped. */ > Is it worth a lockdep check in here on whatever lock is stoping this racing? Yes, it is. Thanks Jonathan. Regards, Terry >> + if (port->uport_regs.ras) >> + return; >> + >> + port->reg_map.host = &port->dev; >> + if (cxl_map_component_regs(&port->reg_map, &port->uport_regs, >> + BIT(CXL_CM_CAP_CAP_ID_RAS))) { >> + dev_err(&port->dev, "Failed to map RAS capability.\n"); >> + return; >> + } >> +} >> +EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, "CXL"); >> + >> /** >> * cxl_dport_init_ras_reporting - Setup CXL RAS report on this dport >> * @dport: the cxl_dport that needs to be initialized >> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h >> index 727429dfdaed..c51735fe75d6 100644 >> --- a/drivers/cxl/cxl.h >> +++ b/drivers/cxl/cxl.h >> @@ -601,6 +601,7 @@ struct cxl_dax_region { >> * @parent_dport: dport that points to this port in the parent >> * @decoder_ida: allocator for decoder ids >> * @reg_map: component and ras register mapping parameters >> + * @uport_regs: mapped component registers >> * @nr_dports: number of entries in @dports >> * @hdm_end: track last allocated HDM decoder instance for allocation ordering >> * @commit_end: cursor to track highest committed decoder for commit ordering >> @@ -621,6 +622,7 @@ struct cxl_port { >> struct cxl_dport *parent_dport; >> struct ida decoder_ida; >> struct cxl_register_map reg_map; >> + struct cxl_component_regs uport_regs; >> int nr_dports; >> int hdm_end; >> int commit_end; >> @@ -773,8 +775,10 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, >> >> #ifdef CONFIG_PCIEAER_CXL >> void cxl_dport_init_ras_reporting(struct cxl_dport *dport); >> +void cxl_uport_init_ras_reporting(struct cxl_port *port); >> #else >> static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport) { } >> +static inline void cxl_uport_init_ras_reporting(struct cxl_port *port) { } >> #endif >> >> struct cxl_decoder *to_cxl_decoder(struct device *dev); >> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c >> index dd39f4565be2..97dbca765f4d 100644 >> --- a/drivers/cxl/mem.c >> +++ b/drivers/cxl/mem.c >> @@ -60,6 +60,7 @@ static bool dev_is_cxl_pci(struct device *dev, u32 pcie_type) >> static void cxl_init_ep_ports_aer(struct cxl_ep *ep) >> { >> struct cxl_dport *dport = ep->dport; >> + struct cxl_port *port = ep->next; >> >> if (dport) { >> struct device *dport_dev = dport->dport_dev; >> @@ -68,6 +69,13 @@ static void cxl_init_ep_ports_aer(struct cxl_ep *ep) >> dev_is_cxl_pci(dport_dev, PCI_EXP_TYPE_ROOT_PORT)) >> cxl_dport_init_ras_reporting(dport); >> } >> + >> + if (port) { >> + struct device *uport_dev = port->uport_dev; >> + >> + if (dev_is_cxl_pci(uport_dev, PCI_EXP_TYPE_UPSTREAM)) >> + cxl_uport_init_ras_reporting(port); >> + } >> } >> >> static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd,