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Tue, 03 Sep 2024 10:45:44 -0700 (PDT) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-717785996d0sm137258b3a.145.2024.09.03.10.45.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 03 Sep 2024 10:45:43 -0700 (PDT) Message-ID: <2f3e01d0-9b4b-4678-b05b-226074579b8a@broadcom.com> Date: Tue, 3 Sep 2024 10:45:41 -0700 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Florian Fainelli Subject: Re: [PATCH v6 07/13] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific To: Bjorn Helgaas , Jim Quinlan Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Stanimir Varbanov , Manivannan Sadhasivam , Krzysztof Kozlowski , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , open list References: <20240902194649.GA224705@bhelgaas> Content-Language: en-US Autocrypt: addr=florian.fainelli@broadcom.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/2/24 12:46, Bjorn Helgaas wrote: > On Thu, Aug 15, 2024 at 06:57:20PM -0400, Jim Quinlan wrote: >> Do prepatory work for the 7712 SoC, which is introduced in a future commit. >> Our HW design has changed two register offsets for the 7712, where >> previously it was a common value for all Broadcom SOCs with PCIe cores. >> Specifically, the two offsets are to the registers HARD_DEBUG and >> INTR2_CPU_BASE. > >> @@ -1499,12 +1502,16 @@ static const int pcie_offsets[] = { >> [RGR1_SW_INIT_1] = 0x9210, >> [EXT_CFG_INDEX] = 0x9000, >> [EXT_CFG_DATA] = 0x9004, >> + [PCIE_HARD_DEBUG] = 0x4204, >> + [PCIE_INTR2_CPU_BASE] = 0x4300, >> }; >> >> static const int pcie_offsets_bmips_7425[] = { >> [RGR1_SW_INIT_1] = 0x8010, >> [EXT_CFG_INDEX] = 0x8300, >> [EXT_CFG_DATA] = 0x8304, >> + [PCIE_HARD_DEBUG] = 0x4204, >> + [PCIE_INTR2_CPU_BASE] = 0x4300, >> }; >> >> static const struct pcie_cfg_data generic_cfg = { >> @@ -1539,6 +1546,8 @@ static const int pcie_offset_bcm7278[] = { >> [RGR1_SW_INIT_1] = 0xc010, >> [EXT_CFG_INDEX] = 0x9000, >> [EXT_CFG_DATA] = 0x9004, >> + [PCIE_HARD_DEBUG] = 0x4204, >> + [PCIE_INTR2_CPU_BASE] = 0x4300, >> }; > > What's the organization scheme here? We now have: > > static const int pcie_offsets[] = { ... }; > static const int pcie_offsets_bmips_7425[] = { ... }; > static const int pcie_offset_bcm7712[] = { ... }; > > static const struct pcie_cfg_data generic_cfg = { ... }; > static const struct pcie_cfg_data bcm7425_cfg = { ... }; > static const struct pcie_cfg_data bcm7435_cfg = { ... }; > static const struct pcie_cfg_data bcm4908_cfg = { ... }; > > static const int pcie_offset_bcm7278[] = { ... }; > > static const struct pcie_cfg_data bcm7278_cfg = { ... }; > static const struct pcie_cfg_data bcm2711_cfg = { ... }; > static const struct pcie_cfg_data bcm7216_cfg = { ... }; > static const struct pcie_cfg_data bcm7712_cfg = { ... }; > > So we have pcie_offsets_bmips_7425[] and pcie_offset_bcm7712[] (with > gratuituously different "offset" vs "offsets") which are all together > before the pcie_cfg_data. > > Then we have pcie_offset_bcm7278[] (again gratuitously different > "offset") separately, next to bcm7278_cfg. > > It would be nice to pick one scheme and stick to it. > > Also a seemingly random order of the pcie_cfg_data structs and > .compatible strings. > > Also a little confusing to have "bmips_7425" and "bcm7425" associated > with the same chip. I suppose there's historical reason for it, but I > don't think it's helpful in this usage. All fair points, especially the lack of consistency, thanks for cleaning that up. -- Florian