From: Wei Huang <wei.huang2@amd.com>
To: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-doc@vger.kernel.org, netdev@vger.kernel.org,
bhelgaas@google.com, corbet@lwn.net, davem@davemloft.net,
edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
alex.williamson@redhat.com, gospo@broadcom.com,
michael.chan@broadcom.com, ajit.khaparde@broadcom.com,
somnath.kotur@broadcom.com, andrew.gospodarek@broadcom.com,
manoj.panicker2@amd.com, Eric.VanTassell@amd.com,
vadim.fedorenko@linux.dev, horms@kernel.org,
bagasdotme@gmail.com
Subject: Re: [PATCH V2 2/9] PCI: Add TPH related register definition
Date: Mon, 10 Jun 2024 15:00:24 -0500 [thread overview]
Message-ID: <3221526e-8698-4930-81e6-715cf3f1a18f@amd.com> (raw)
In-Reply-To: <20240607171716.0000216d@Huawei.com>
On 6/7/24 11:17, Jonathan Cameron wrote:
> On Fri, 31 May 2024 16:38:34 -0500
> Wei Huang <wei.huang2@amd.com> wrote:
>> /* TPH Requester */
>> #define PCI_TPH_CAP 4 /* capability register */
>> +#define PCI_TPH_CAP_NO_ST 0x1 /* no ST mode supported */
>> +#define PCI_TPH_CAP_NO_ST_SHIFT 0x0 /* no ST mode supported shift */
>> +#define PCI_TPH_CAP_INT_VEC 0x2 /* interrupt vector mode supported */
>> +#define PCI_TPH_CAP_INT_VEC_SHIFT 0x1 /* interrupt vector mode supported shift */
>> +#define PCI_TPH_CAP_DS 0x4 /* device specific mode supported */
>> +#define PCI_TPH_CAP_DS_SHIFT 0x4 /* device specific mode supported shift */
>> #define PCI_TPH_CAP_LOC_MASK 0x600 /* location mask */
>> -#define PCI_TPH_LOC_NONE 0x000 /* no location */
>> -#define PCI_TPH_LOC_CAP 0x200 /* in capability */
>> -#define PCI_TPH_LOC_MSIX 0x400 /* in MSI-X */
>
> It's a userspace header, relatively unlikely to be safe to change it...
> This would also be inconsistent with how some other registers are defined in here.
>
> I'd love it if we could tidy this up, but we are stuck by this being
> in uapi.
Alex Williamson had a similar comment in another email. In V3, I will
only add (necessary) new definitions and refrain from touching the
existing ones.
next prev parent reply other threads:[~2024-06-10 20:00 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-31 21:38 [PATCH V2 0/9] PCIe TPH and cache direct injection support Wei Huang
2024-05-31 21:38 ` [PATCH V2 1/9] PCI: Introduce PCIe TPH support framework Wei Huang
2024-06-07 15:56 ` Jonathan Cameron
2024-06-07 16:27 ` Bjorn Helgaas
2024-05-31 21:38 ` [PATCH V2 2/9] PCI: Add TPH related register definition Wei Huang
2024-06-07 16:17 ` Jonathan Cameron
2024-06-10 20:00 ` Wei Huang [this message]
2024-06-07 16:42 ` Bjorn Helgaas
2024-06-10 20:04 ` Wei Huang
2024-05-31 21:38 ` [PATCH V2 3/9] PCI/TPH: Implement a command line option to disable TPH Wei Huang
2024-06-07 16:27 ` Jonathan Cameron
2024-06-07 19:59 ` Bjorn Helgaas
2024-05-31 21:38 ` [PATCH V2 4/9] PCI/TPH: Implement a command line option to force No ST Mode Wei Huang
2024-06-07 16:32 ` Jonathan Cameron
2024-06-07 17:42 ` Bjorn Helgaas
2024-05-31 21:38 ` [PATCH V2 5/9] PCI/TPH: Introduce API functions to manage steering tags Wei Huang
2024-06-06 22:30 ` kernel test robot
2024-06-07 17:29 ` Jonathan Cameron
2024-06-07 17:45 ` Bjorn Helgaas
2024-05-31 21:38 ` [PATCH V2 6/9] PCI/TPH: Retrieve steering tag from ACPI _DSM Wei Huang
2024-06-04 15:30 ` Simon Horman
2024-06-05 19:34 ` Wei Huang
2024-06-07 17:39 ` Jonathan Cameron
2024-06-07 18:43 ` Bjorn Helgaas
2024-05-31 21:38 ` [PATCH V2 7/9] PCI/TPH: Add TPH documentation Wei Huang
2024-06-07 17:43 ` Jonathan Cameron
2024-05-31 21:38 ` [PATCH V2 8/9] bnxt_en: Add TPH support in BNXT driver Wei Huang
2024-05-31 21:38 ` [PATCH V2 9/9] bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings Wei Huang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3221526e-8698-4930-81e6-715cf3f1a18f@amd.com \
--to=wei.huang2@amd.com \
--cc=Eric.VanTassell@amd.com \
--cc=Jonathan.Cameron@Huawei.com \
--cc=ajit.khaparde@broadcom.com \
--cc=alex.williamson@redhat.com \
--cc=andrew.gospodarek@broadcom.com \
--cc=bagasdotme@gmail.com \
--cc=bhelgaas@google.com \
--cc=corbet@lwn.net \
--cc=davem@davemloft.net \
--cc=edumazet@google.com \
--cc=gospo@broadcom.com \
--cc=horms@kernel.org \
--cc=kuba@kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=manoj.panicker2@amd.com \
--cc=michael.chan@broadcom.com \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=somnath.kotur@broadcom.com \
--cc=vadim.fedorenko@linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox