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(2001-1c00-0c32-7800-5bfa-a036-83f0-f9ec.cable.dynamic.v6.ziggo.nl. [2001:1c00:c32:7800:5bfa:a036:83f0:f9ec]) by smtp.gmail.com with ESMTPSA id s2-20020a1709066c8200b009e656ce2930sm3712141ejr.60.2023.11.20.02.13.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Nov 2023 02:13:41 -0800 (PST) Message-ID: <32a73a9d-812c-47b5-9de7-95c77ce028b5@redhat.com> Date: Mon, 20 Nov 2023 11:13:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/4] Add support for drivers to decide bridge D3 policy Content-Language: en-US, nl To: Mario Limonciello , Bjorn Helgaas , =?UTF-8?Q?Ilpo_J=C3=A4rvinen?= Cc: "Rafael J . Wysocki" , Shyam Sundar S K , "open list:PCI SUBSYSTEM" , "open list:X86 PLATFORM DRIVERS" , Lukas Wunner , Kai-Heng Feng References: <20231025020546.504-1-mario.limonciello@amd.com> From: Hans de Goede In-Reply-To: <20231025020546.504-1-mario.limonciello@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi, On 10/25/23 04:05, Mario Limonciello wrote: > The policy for whether PCI bridges are allowed to select D3 is dictated > by empirical results that are enumerated into pci_bridge_d3_possible(). > > In Windows this behaves differently in that Windows internal policy is > not used for devices when a power engine plugin driver provided by the > SOC vendor is installed. This driver is used to decide the policy in > those cases. > > This series implements a system that lets drivers register such a policy > control as well. It isn't activated for any SOCs by default. I must admit that I've lost track of the status of this series... With that said patch 4/4 looks good to me and I believe that if this series gets accepted it will be best to send 4/4 upstream together with the rest through some other tree then the the pdx86 tree. So here is my ack for sending a future version of patch 4/4 ("platform/x86/amd: pmc: Add support for using constraints to decide D3 policy") upstream through another subsystem tree: Acked-by: Hans de Goede Regards, Hans > This is heavily leveraged from the work in [1] > > [1] https://lore.kernel.org/platform-driver-x86/20230906184354.45846-1-mario.limonciello@amd.com/ > > RFC v1->PATCH v1 > * Simplify the logic, use pci_d3cold_enable()/pci_d3cold_disable() functions > * Roll https://lore.kernel.org/linux-pci/20231004144731.158342-1-mario.limonciello@amd.com/ into series > * Updates for some typos > * Re-order series. Patches 1 and 2 can potentially apply to PCI tree, 3 and 4 to platform-x86 tree. > > Mario Limonciello (4): > PCI: Make d3cold_allowed sysfs attribute read only > PCI: Refresh root ports in pci_bridge_d3_update() > ACPI: x86: s2idle: Export symbol for fetching constraints for module > use > platform/x86/amd: pmc: Add support for using constraints to decide D3 > policy > > Documentation/ABI/testing/sysfs-bus-pci | 4 +- > drivers/acpi/x86/s2idle.c | 1 + > drivers/pci/pci-acpi.c | 2 +- > drivers/pci/pci-sysfs.c | 14 +----- > drivers/pci/pci.c | 12 ++++-- > drivers/platform/x86/amd/pmc/pmc.c | 57 +++++++++++++++++++++++++ > include/linux/pci.h | 1 - > 7 files changed, 72 insertions(+), 19 deletions(-) >