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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-abb9553fbd0sm310488366b.84.2025.02.17.12.37.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Feb 2025 12:37:28 -0800 (PST) Message-ID: <33f5d722-da5d-4b9b-bddf-922e820d8b7a@oss.qualcomm.com> Date: Mon, 17 Feb 2025 21:37:25 +0100 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 6/6] arm64: dts: qcom: sm8450: add PCIe EP device nodes To: Dmitry Baryshkov , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Mrinmay Sarkar , Bjorn Andersson , Konrad Dybcio Cc: =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250217-sar2130p-pci-v1-0-94b20ec70a14@linaro.org> <20250217-sar2130p-pci-v1-6-94b20ec70a14@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250217-sar2130p-pci-v1-6-94b20ec70a14@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: Cwar-NbVnnApWAOpPxym-GxH9SZqWJTE X-Proofpoint-GUID: Cwar-NbVnnApWAOpPxym-GxH9SZqWJTE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-17_08,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 mlxscore=0 suspectscore=0 adultscore=0 clxscore=1015 impostorscore=0 bulkscore=0 mlxlogscore=936 lowpriorityscore=0 spamscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502170161 On 17.02.2025 7:56 PM, Dmitry Baryshkov wrote: > On the Qualcomm SM8450 platform the second PCIe host can be used > either as an RC or as an EP device. Add device node for the PCIe EP. > > Signed-off-by: Dmitry Baryshkov > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 52 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 52 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 9c809fc5fa45a98ff5441a0b6809931588897243..ad0ec15b18e5ca7bea196be1564152f7faf51d9f 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -2262,6 +2262,58 @@ pcie@0 { > }; > }; > > + pcie1_ep: pcie-ep@1c08000 { > + compatible = "qcom,sm8450-pcie-ep"; > + reg = <0x0 0x01c08000 0x0 0x3000>, > + <0x0 0x40000000 0x0 0xf1d>, > + <0x0 0x40000f20 0x0 0xa8>, > + <0x0 0x40001000 0x0 0x1000>, > + <0x0 0x40200000 0x0 0x1000000>, > + <0x0 0x01c0b000 0x0 0x1000>, > + <0x0 0x40002000 0x0 0x1000>; > + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", > + "mmio", "dma"; > + > + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, > + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a", > + "ref", > + "ddrss_sf_tbu", > + "aggre_noc_axi"; > + > + interrupts = , > + , > + ; > + interrupt-names = "global", "doorbell", "dma"; > + > + interconnects = <&pcie_noc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>; same comments as patch 5, plus please use tags Konrad