From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m49241.qiye.163.com (mail-m49241.qiye.163.com [45.254.49.241]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 489BA32D450; Thu, 16 Oct 2025 10:00:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.254.49.241 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760608843; cv=none; b=LDXvePj0NYYM8dZYfNMiK2Jah6kmfgbXMb3gsmGZ682+WOPyNQoKGMD6RFp0Am26FsLfrzOYT+2fUTaHV6UzgGT4UHa26OtAelmZWYXJLjw1ElAf+46aBbYBWlWw061ZWlJ6yhvZUC9azrd1JEEATdiG8B2nHP/Yfpk/DMfm7ig= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760608843; c=relaxed/simple; bh=L6laFqRaWSI17Vo5SosZbjACISiZSTJZPRWTW2IBLRk=; h=Message-ID:Date:MIME-Version:Cc:Subject:To:References:From: In-Reply-To:Content-Type; b=FAJCR/vfRvaf7QMdT4kiqyi6zk3DyFS7SLvSlS8JKihE2FIGAfLOQOCNz92OL+ByXXBbC4k3hCg6qz9zuWAUCpOMqsBsuly68qx2gprxaOm3Dbr3JEDKS578hp1ycSh0p2/Eqk+Q6KNKlryPbkvPeK8CThrQHw0yOGYg1Fh1/BE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=Dkg1ccWx; arc=none smtp.client-ip=45.254.49.241 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="Dkg1ccWx" Received: from [172.16.12.129] (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 262323a9f; Thu, 16 Oct 2025 18:00:28 +0800 (GMT+08:00) Message-ID: <3470351f-88ab-48bb-97af-dde4e6eba938@rock-chips.com> Date: Thu, 16 Oct 2025 18:00:24 +0800 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Cc: shawn.lin@rock-chips.com, Damien Le Moal , Dragan Simic , FUKAUMI Naoki , Diederik de Haas , stable@vger.kernel.org, Manivannan Sadhasivam , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH v2] PCI: dw-rockchip: Disable L1 substates To: Niklas Cassel , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Kever Yang , Simon Xue References: <20251016090422.451982-2-cassel@kernel.org> From: Shawn Lin In-Reply-To: <20251016090422.451982-2-cassel@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-HM-Tid: 0a99ec76ba4d09cckunmc3027d237c39a4 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZGkNKTlZJT0hPSE4ZHx9IQ0xWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSU9PT0 hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=Dkg1ccWxhcEzQTOcTY7bf6wuAXYywd+hMTvRqDxRE1vMLe89yV6Etd0r4HtjD7Lib8ucQ/xO9ILeS0kR9IRcb4AfFbQ7Zq1l5oLWraylks88KcjFaIB10gPecPxyug1hiVMXiTxry8XoDnCwbI/lCmmSFioxp53oLomGc7999KY=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=kN3t/e7sa1Sb2IowRbuDgju83rFZL2AXB/0qfNEujok=; h=date:mime-version:subject:message-id:from; 在 2025/10/16 星期四 17:04, Niklas Cassel 写道: > The L1 substates support requires additional steps to work, see e.g. > section '11.6.6.4 L1 Substate' in the RK3588 TRM V1.0. > > These steps are currently missing from the driver. Yes, we could add them later if concerns about supports-clkreq is fully discussed. > > While this has always been a problem when using e.g. > CONFIG_PCIEASPM_POWER_SUPERSAVE=y, the problem became more apparent after > commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for > devicetree platforms"), which enabled ASPM also for > CONFIG_PCIEASPM_DEFAULT=y. > > Disable L1 substates until proper support is added. > Thanks for the patch. Acked-by: Shawn Lin > Cc: stable@vger.kernel.org > Fixes: 0e898eb8df4e ("PCI: rockchip-dwc: Add Rockchip RK356X host controller driver") > Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms") > Signed-off-by: Niklas Cassel > --- > Changes since v1: > -Remove superfluous dw_pcie_readl_dbi() > > drivers/pci/controller/dwc/pcie-dw-rockchip.c | 21 +++++++++++++++++++ > 1 file changed, 21 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > index 3e2752c7dd09..84f882abbca5 100644 > --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c > +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c > @@ -200,6 +200,25 @@ static bool rockchip_pcie_link_up(struct dw_pcie *pci) > return FIELD_GET(PCIE_LINKUP_MASK, val) == PCIE_LINKUP; > } > > +/* > + * See e.g. section '11.6.6.4 L1 Substate' in the RK3588 TRM V1.0 for the steps > + * needed to support L1 substates. Currently, not a single rockchip platform > + * performs these steps, so disable L1 substates until there is proper support. > + */ > +static void rockchip_pcie_disable_l1sub(struct dw_pcie *pci) > +{ > + u32 cap, l1subcap; > + > + cap = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); > + if (cap) { > + l1subcap = dw_pcie_readl_dbi(pci, cap + PCI_L1SS_CAP); > + l1subcap &= ~(PCI_L1SS_CAP_L1_PM_SS | PCI_L1SS_CAP_ASPM_L1_1 | > + PCI_L1SS_CAP_ASPM_L1_2 | PCI_L1SS_CAP_PCIPM_L1_1 | > + PCI_L1SS_CAP_PCIPM_L1_2); > + dw_pcie_writel_dbi(pci, cap + PCI_L1SS_CAP, l1subcap); > + } > +} > + > static void rockchip_pcie_enable_l0s(struct dw_pcie *pci) > { > u32 cap, lnkcap; > @@ -264,6 +283,7 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp) > irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler, > rockchip); > > + rockchip_pcie_disable_l1sub(pci); > rockchip_pcie_enable_l0s(pci); > > return 0; > @@ -301,6 +321,7 @@ static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep) > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > enum pci_barno bar; > > + rockchip_pcie_disable_l1sub(pci); > rockchip_pcie_enable_l0s(pci); > rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep); >