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Fri, 15 Nov 2024 18:15:43 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4AFIFg6x027723 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 15 Nov 2024 18:15:42 GMT Received: from [10.110.68.79] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 15 Nov 2024 10:15:40 -0800 Message-ID: <362bbb66-3d8b-4b20-9e02-1cbe234510c6@quicinc.com> Date: Fri, 15 Nov 2024 10:15:39 -0800 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/4] PCI: dwc: Export dwc MSI controller related APIs To: Manivannan Sadhasivam CC: , , , , , , , , , , References: <20241106221341.2218416-1-quic_mrana@quicinc.com> <20241106221341.2218416-2-quic_mrana@quicinc.com> <20241115091419.tc4p2jwukjdo56of@thinkpad> Content-Language: en-US From: Mayank Rana In-Reply-To: <20241115091419.tc4p2jwukjdo56of@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: MD9u7n5VoT62-OZrVRUDqXzF1fpVhvgr X-Proofpoint-GUID: MD9u7n5VoT62-OZrVRUDqXzF1fpVhvgr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 clxscore=1015 adultscore=0 mlxlogscore=999 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2411150153 On 11/15/2024 1:14 AM, Manivannan Sadhasivam wrote: > On Wed, Nov 06, 2024 at 02:13:38PM -0800, Mayank Rana wrote: >> To allow dwc PCIe controller based MSI functionality from ECAM pcie >> driver, export dw_pcie_msi_host_init(), dw_pcie_msi_init() and >> dw_pcie_msi_free() APIs. Also move MSI IRQ related initialization code >> into dw_pcie_msi_init() as this code executes before dw_pcie_msi_init() >> API to use with ECAM driver. >> >> Signed-off-by: Mayank Rana >> --- >> .../pci/controller/dwc/pcie-designware-host.c | 38 ++++++++++--------- >> drivers/pci/controller/dwc/pcie-designware.h | 14 +++++++ >> 2 files changed, 34 insertions(+), 18 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c >> index 3e41865c7290..25020a090db8 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware-host.c >> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c >> @@ -250,7 +250,7 @@ int dw_pcie_allocate_domains(struct dw_pcie_rp *pp) >> return 0; >> } >> >> -static void dw_pcie_free_msi(struct dw_pcie_rp *pp) >> +void dw_pcie_free_msi(struct dw_pcie_rp *pp) >> { >> u32 ctrl; >> >> @@ -263,19 +263,34 @@ static void dw_pcie_free_msi(struct dw_pcie_rp *pp) >> irq_domain_remove(pp->msi_domain); >> irq_domain_remove(pp->irq_domain); >> } >> +EXPORT_SYMBOL_GPL(dw_pcie_free_msi); >> >> -static void dw_pcie_msi_init(struct dw_pcie_rp *pp) >> +void dw_pcie_msi_init(struct dw_pcie_rp *pp) >> { >> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> u64 msi_target = (u64)pp->msi_data; >> + u32 ctrl, num_ctrls; >> >> if (!pci_msi_enabled() || !pp->has_msi_ctrl) >> return; >> >> + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; >> + >> + /* Initialize IRQ Status array */ >> + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { >> + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + >> + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), >> + pp->irq_mask[ctrl]); >> + dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + >> + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), >> + ~0); >> + } >> + >> /* Program the msi_data */ >> dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target)); >> dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target)); >> } >> +EXPORT_SYMBOL_GPL(dw_pcie_msi_init); >> >> static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) >> { >> @@ -317,7 +332,7 @@ static int dw_pcie_parse_split_msi_irq(struct dw_pcie_rp *pp) >> return 0; >> } >> >> -static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) >> +int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) >> { >> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> struct device *dev = pci->dev; >> @@ -391,6 +406,7 @@ static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) >> >> return 0; >> } >> +EXPORT_SYMBOL_GPL(dw_pcie_msi_host_init); >> >> static void dw_pcie_host_request_msg_tlp_res(struct dw_pcie_rp *pp) >> { >> @@ -802,7 +818,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) >> int dw_pcie_setup_rc(struct dw_pcie_rp *pp) >> { >> struct dw_pcie *pci = to_dw_pcie_from_pp(pp); >> - u32 val, ctrl, num_ctrls; >> + u32 val; >> int ret; >> >> /* >> @@ -813,20 +829,6 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) >> >> dw_pcie_setup(pci); >> >> - if (pp->has_msi_ctrl) { >> - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; >> - >> - /* Initialize IRQ Status array */ >> - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { >> - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_MASK + >> - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), >> - pp->irq_mask[ctrl]); >> - dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_ENABLE + >> - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), >> - ~0); >> - } >> - } >> - >> dw_pcie_msi_init(pp); >> >> /* Setup RC BARs */ >> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h >> index 347ab74ac35a..ef748d82c663 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.h >> +++ b/drivers/pci/controller/dwc/pcie-designware.h >> @@ -679,6 +679,9 @@ static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci) >> >> #ifdef CONFIG_PCIE_DW_HOST >> irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); >> +void dw_pcie_msi_init(struct dw_pcie_rp *pp); >> +int dw_pcie_msi_host_init(struct dw_pcie_rp *pp); >> +void dw_pcie_free_msi(struct dw_pcie_rp *pp); >> int dw_pcie_setup_rc(struct dw_pcie_rp *pp); >> int dw_pcie_host_init(struct dw_pcie_rp *pp); >> void dw_pcie_host_deinit(struct dw_pcie_rp *pp); >> @@ -691,6 +694,17 @@ static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp) >> return IRQ_NONE; >> } >> >> +static void dw_pcie_msi_init(struct dw_pcie_rp *pp) > > Missing 'inline' here and below? ACK > > - Mani > >> +{ } >> + >> +static int dw_pcie_msi_host_init(struct dw_pcie_rp *pp) >> +{ >> + return -ENODEV; >> +} >> + >> +static void dw_pcie_free_msi(struct dw_pcie_rp *pp) >> +{ } >> + >> static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp) >> { >> return 0; >> -- >> 2.25.1 >> >