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Wed, 29 Oct 2025 20:43:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEG8Tsm7zsMNvRb42NpHg0S5cqbhX8hvTZ+lzZFtUmt1DssbzW9YgQ30jiCbWgwAcLvsjL2Pw== X-Received: by 2002:a17:902:d487:b0:290:c07f:e8ee with SMTP id d9443c01a7336-294deee23a3mr66506845ad.43.1761795819628; Wed, 29 Oct 2025 20:43:39 -0700 (PDT) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29498d2333fsm166960675ad.50.2025.10.29.20.43.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 29 Oct 2025 20:43:39 -0700 (PDT) Message-ID: <3dccca2d-272f-451a-9e38-901a6fa3a24c@oss.qualcomm.com> Date: Thu, 30 Oct 2025 09:13:29 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 0/8] PCI: Enable Power and configure the TC9563 PCIe switch To: Bjorn Helgaas Cc: Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof Kozlowski , Conor Dooley , chaitanya chundru , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, Jingoo Han , Bartosz Golaszewski , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Catalin Marinas , Will Deacon , amitk@kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, jorge.ramirez@oss.qualcomm.com, linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov , Dmitry Baryshkov , Bartosz Golaszewski References: <20251029232323.GA1602660@bhelgaas> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20251029232323.GA1602660@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDMwMDAyNyBTYWx0ZWRfXxqdg7QMDZ1bC SFtEbf7OjYev2gTAy0Y09qDJBDjX1DJJijxKB/H3ImPu+buem0ECYM0gqdiIyYxA+l6pZRE2jqm xq/hUqVnqBl52RNzfZuZrzS1if7i8DHKg5FrUcLlbAFip8ZrBMM+1VkN/q8waiLQoCPk2rIlnA8 Fc9QGnd9p5IesK2D001jCDCoEY4oC7LVAwF/UMsjnY1MWP1vZA4RAxe0Z4rkppmai1FK9sgdQqu TbT3B5M2LvZ2SX+p7o7XGjKNlbRN5Jk4cocE3AbKkhYqq4Z2tBL5rWD+Ffbobid14PSgrTs4+Tl j3Tl/x8nMGB1UxoH0CdEp8F3r+BHZbBhF1ENeMnKRaG2RZn4gZ4U5EKuKib1792CI10SnjBaRQw 0lLxZ0VMTYSpzVh8MDlHye7zBA9VVg== X-Proofpoint-ORIG-GUID: CmbDytuL3Sg2kBTdBH-Jh1FJlKtBMqmq X-Authority-Analysis: v=2.4 cv=V+RwEOni c=1 sm=1 tr=0 ts=6902deed cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=FxhApbZLZ_QfhaJha3gA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: CmbDytuL3Sg2kBTdBH-Jh1FJlKtBMqmq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-10-30_01,2025-10-29_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 suspectscore=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2510300027 On 10/30/2025 4:53 AM, Bjorn Helgaas wrote: > On Wed, Oct 29, 2025 at 04:59:53PM +0530, Krishna Chaitanya Chundru wrote: >> TC9563 is the PCIe switch which has one upstream and three downstream >> ports. To one of the downstream ports ethernet MAC is connected as endpoint >> device. Other two downstream ports are supposed to connect to external >> device. One Host can connect to TC956x by upstream port. >> >> TC9563 switch power is controlled by the GPIO's. After powering on >> the switch will immediately participate in the link training. if the >> host is also ready by that time PCIe link will established. >> >> The TC9563 needs to configured certain parameters like de-emphasis, >> disable unused port etc before link is established. >> >> As the controller starts link training before the probe of pwrctl driver, >> the PCIe link may come up as soon as we power on the switch. Due to this >> configuring the switch itself through i2c will not have any effect as >> this configuration needs to done before link training. To avoid this >> introduce two functions in pci_ops to start_link() & stop_link() which >> will disable the link training if the PCIe link is not up yet. >> >> This series depends on the https://lore.kernel.org/all/20250124101038.3871768-3-krishna.chundru@oss.qualcomm.com/ > What does this series apply to? It doesn't apply cleanly to v6.18-rc1 > (the normal base for topic branches) or v6.18-rc3 or pci/next. I sent this on top of rc3 as we have some dependencies with latest changes i.e ecam changes in dwc driver. > I tried first applying the patches from > https://lore.kernel.org/all/20250124101038.3871768-3-krishna.chundru@oss.qualcomm.com/, > but those don't apply to -rc1 or -rc3 either. This needs to be applied on the dts schema in github, it is already applied I will remove this reference in next series. - Krishna Chaitanya. > > Bjorn