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From: duziming <duziming2@huawei.com>
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: David Laight <david.laight.linux@gmail.com>,
	<bhelgaas@google.com>, <linux-pci@vger.kernel.org>,
	LKML <linux-kernel@vger.kernel.org>, <liuyongqiang13@huawei.com>
Subject: Re: [PATCH v3 3/3] PCI/sysfs: Prohibit unaligned access to I/O port on non-x86
Date: Fri, 9 Jan 2026 17:40:06 +0800	[thread overview]
Message-ID: <422df374-2afd-48c0-be73-834ce95fb55c@huawei.com> (raw)
In-Reply-To: <0d57b385-410f-3296-ca8b-8b1370a886b1@linux.intel.com>


在 2026/1/9 15:21, Ilpo Järvinen 写道:
> On Thu, 8 Jan 2026, duziming wrote:
>
>> 在 2026/1/8 16:56, David Laight 写道:
>>> On Thu, 8 Jan 2026 09:59:44 +0800
>>> Ziming Du <duziming2@huawei.com> wrote:
>>>
>>>> From: Yongqiang Liu <liuyongqiang13@huawei.com>
>>>>
>>>> Unaligned access is harmful for non-x86 archs such as arm64. When we
>>>> use pwrite or pread to access the I/O port resources with unaligned
>>>> offset, system will crash as follows:
>>>>
>>>> Unable to handle kernel paging request at virtual address fffffbfffe8010c1
>>>> Internal error: Oops: 0000000096000061 [#1] SMP
>>>> Call trace:
>>>>    _outw include/asm-generic/io.h:594 [inline]
>>>>    logic_outw+0x54/0x218 lib/logic_pio.c:305
>>>>    pci_resource_io drivers/pci/pci-sysfs.c:1157 [inline]
>>>>    pci_write_resource_io drivers/pci/pci-sysfs.c:1191 [inline]
>>>>    pci_write_resource_io+0x208/0x260 drivers/pci/pci-sysfs.c:1181
>>>>    sysfs_kf_bin_write+0x188/0x210 fs/sysfs/file.c:158
>>>>    kernfs_fop_write_iter+0x2e8/0x4b0 fs/kernfs/file.c:338
>>>>    vfs_write+0x7bc/0xac8 fs/read_write.c:586
>>>>    ksys_write+0x12c/0x270 fs/read_write.c:639
>>>>    __arm64_sys_write+0x78/0xb8 fs/read_write.c:648
>>>>
>>>> Powerpc seems affected as well, so prohibit the unaligned access
>>>> on non-x86 archs.
>>> I'm not sure it makes any real sense for x86 either.
>>> IIRC io space is just like memory space, so a 16bit io access looks the
>>> same as two 8bit accesses to an 8bit device (some put the 'data fifo' on
>>> addresses 0 and 1 so the code could use 16bit io accesses to speed things
>>> up).
>>> The same will have applied to misaligned accesses.
>>> But, in reality, all device registers are aligned.
>>>
>>> I'm not sure EFAULT is the best error code though, EINVAL might be better.
>>> (EINVAL is returned for other address/size errors.)
>>> EFAULT is usually returned for errors accessing the user buffer, a least
>>> one unix system raises SIGSEGV whenever EFAULT is returned.
>>>
>> Just to confirm: should all architectures prohibit unaligned access to device
>> registers?
> In my opinion, yes, also x86 should prohibit it (like I already
> expressed but you ignored that comment until now).
Oops,  I didn’t quite understand your opinion earlier :(
>

  reply	other threads:[~2026-01-09  9:40 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-08  1:59 [PATCH v3 0/3] Miscellaneous fixes for pci subsystem Ziming Du
2026-01-08  1:59 ` [PATCH v3 1/3] PCI/sysfs: Fix null pointer dereference during hotplug Ziming Du
2026-01-08  1:59 ` [PATCH v3 2/3] PCI: Prevent overflow in proc_bus_pci_write() Ziming Du
2026-01-08 11:35   ` Ilpo Järvinen
2026-01-08  1:59 ` [PATCH v3 3/3] PCI/sysfs: Prohibit unaligned access to I/O port on non-x86 Ziming Du
2026-01-08  8:56   ` David Laight
2026-01-08 11:49     ` duziming
2026-01-09  7:21       ` Ilpo Järvinen
2026-01-09  9:40         ` duziming [this message]
2026-01-09  0:38     ` Maciej W. Rozycki
2026-01-09 12:53       ` David Laight
2026-01-09 15:25         ` Maciej W. Rozycki

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