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(2001-1c00-0c1e-bf00-d69d-5353-dba5-ee81.cable.dynamic.v6.ziggo.nl. [2001:1c00:c1e:bf00:d69d:5353:dba5:ee81]) by smtp.gmail.com with ESMTPSA id u20-20020a509514000000b0042dd1d3d571sm5678676eda.26.2022.06.13.13.31.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Jun 2022 13:31:40 -0700 (PDT) Message-ID: <45d458f5-4f4e-9ebd-cb51-1a7b784248ec@redhat.com> Date: Mon, 13 Jun 2022 22:31:39 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH v1 1/1] x86/PCI: Disable e820 usage for the resource allocation Content-Language: en-US To: Andy Shevchenko , "Gustavo A. R. Silva" , Bjorn Helgaas , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Ferry Toth References: <20220613201641.67640-1-andriy.shevchenko@linux.intel.com> From: Hans de Goede In-Reply-To: <20220613201641.67640-1-andriy.shevchenko@linux.intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi, On 6/13/22 22:16, Andy Shevchenko wrote: > The resource management improve for PCI on x86 broke booting of Intel MID > platforms. It seems that the current code removes all available resources > from the list and none of the PCI device may be initialized. Restore the > old behaviour by force disabling the e820 usage for the resource allocation. > > Fixes: 4c5e242d3e93 ("x86/PCI: Clip only host bridge windows for E820 regions") > Depends-on: fa6dae5d8208 ("x86/PCI: Add kernel cmdline options to use/ignore E820 reserved regions") > Signed-off-by: Andy Shevchenko Andy, thank you for the patch. Commit 4c5e242d3e93 has also been causing issues for other platforms, so I've submitted a revert of it here: https://lore.kernel.org/linux-pci/20220612144325.85366-1-hdegoede@redhat.com/T/#u can you please give the revert a try, and confirm that that fixes the Intel MID platform issue too ? Regards, Hans > --- > arch/x86/include/asm/pci_x86.h | 1 + > arch/x86/pci/acpi.c | 2 +- > arch/x86/pci/intel_mid_pci.c | 1 + > 3 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h > index f52a886d35cf..503f83fbc686 100644 > --- a/arch/x86/include/asm/pci_x86.h > +++ b/arch/x86/include/asm/pci_x86.h > @@ -126,6 +126,7 @@ extern const struct pci_raw_ops *raw_pci_ext_ops; > extern const struct pci_raw_ops pci_mmcfg; > extern const struct pci_raw_ops pci_direct_conf1; > extern bool port_cf9_safe; > +extern bool pci_use_e820; > > /* arch_initcall level */ > #ifdef CONFIG_PCI_DIRECT > diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c > index a4f43054bc79..ac2f220d50fc 100644 > --- a/arch/x86/pci/acpi.c > +++ b/arch/x86/pci/acpi.c > @@ -20,7 +20,7 @@ struct pci_root_info { > #endif > }; > > -static bool pci_use_e820 = true; > +bool pci_use_e820 = true; > static bool pci_use_crs = true; > static bool pci_ignore_seg; > > diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c > index 8edd62206604..7869b86bff04 100644 > --- a/arch/x86/pci/intel_mid_pci.c > +++ b/arch/x86/pci/intel_mid_pci.c > @@ -313,6 +313,7 @@ int __init intel_mid_pci_init(void) > pcibios_enable_irq = intel_mid_pci_irq_enable; > pcibios_disable_irq = intel_mid_pci_irq_disable; > pci_root_ops = intel_mid_pci_ops; > + pci_use_e820 = false; > pci_soc_mode = 1; > /* Continue with standard init */ > acpi_noirq_set();