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Fri, 19 Sep 2025 15:30:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1758288620; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IURTeqqTjduSTnwx7LDzSNH9H6AyP3UiSbRBPX8HLUo=; b=UwZH8Wkwb1hAk3bfC6+nUFe13NHpC+cIn4QasCtH6MmlDAUwA0mIJZtsX1nGblILYTgbJk XXNxH4AgZ89NI6z7Fdh3qBjXSrrZ6+EFjnUO261dloAOZOgIvr2BV9PRxvhc8gQzW/EWz9 p6VnOr9jAKc8CZg+7g1hbDN5XRF2gSCmWrLVEcfAL+Z9iJ/9UAXslu8cpJ8h8fTEfcZhYy pLWxbYoUCNsG1To2TIMCdhRlddgtkUIAPoASu5pg4nrO56rdwwRNhcEFCN8m5XHMkOdTjd wwp0pOsEmmKFdDD4DPkbGhh4U8l3WhfqmbDUYKES97BAEF1kOs9w0CUqpnhZ1g== Message-ID: <475cfd27-54d2-44b3-9b26-5de4b75033ff@mailbox.org> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1758288618; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IURTeqqTjduSTnwx7LDzSNH9H6AyP3UiSbRBPX8HLUo=; b=Is6FkuHYwvAr7/ph+xvdYFzXK/2fFYI+Upi/4cydhh2gfPnfJRJfAPUqNTX9fKz08ENC0R 3A0rwVydBzfIQVxfT75OrmJf5MTY6d8G9yHJrKbs1ekXVBAP4x1J9xfIc3hVPVu00lo9CR fl99+qx9Gl0lbbLrdeCdYkSXwyrgDAjGyG8I0YBl4RGnzEYq22f1Yu95Lm1ryVR65HOZ9V f7E5twIc3EDiAB1tuOaUVsJu4oG8QbGjq3wfzrJkYu/6lAaScs8fDaav9Ie711Q0iwzXhx tKGs0XE0A/Ugreqhx7d/c2rYD0UA5V4V+YuBtg09D+/eLYLrQEBHSANUm4ZUyQ== Date: Fri, 19 Sep 2025 15:30:14 +0200 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Subject: Re: [PATCH v2] PCI: rcar-gen4: Add missing 1ms delay after PWR reset assertion To: Manivannan Sadhasivam , Marek Vasut , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= Cc: linux-pci@vger.kernel.org, Geert Uytterhoeven , Bjorn Helgaas , Geert Uytterhoeven , Lorenzo Pieralisi , Magnus Damm , Rob Herring , Yoshihiro Shimoda , linux-renesas-soc@vger.kernel.org References: <20250918231253.189906-1-marek.vasut+renesas@mailbox.org> <20250919100038.GA3918632@rocinante> <3h3tkv6jmkwqqsb6bdotdx4bcnnzqqqzgl5digryxo5bc4qpm6@np76zatxj6ff> Content-Language: en-US From: Marek Vasut In-Reply-To: <3h3tkv6jmkwqqsb6bdotdx4bcnnzqqqzgl5digryxo5bc4qpm6@np76zatxj6ff> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-MBO-RS-ID: fb68b355c9e47a5e3f5 X-MBO-RS-META: 45qi1xcbz9enx5o1c8hdcmzec4qf4jxn On 9/19/25 2:33 PM, Manivannan Sadhasivam wrote: Hello Manivannan, >>> Because it is the controller driver which can determine whether or not the >>> controller is in HSC domain based on its compatible string, add the missing >>> delay into the controller driver. >>> >>> This 1ms delay is documented on R-Car V4H and V4M, it is currently unclear >>> whether S4 is affected as well. This patch does apply the extra delay on >>> R-Car S4 as well. >> > > What are the implications of not having the delay? Just asking to determine if > this patch is a stable candidate or not. Observable, thus far, none. However, the current behavior does not follow the reference manual operations chart, so I think this should be in stable, else the hardware is operated out of specification. >> [...] >>> - if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) >>> + if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) { >>> reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc); >>> + fsleep(1000); >>> + } >> >> Would it be a prudent thing to do here to add a comment over the fsleep() >> or over the if-statement to document briefly (and for posterity) why we >> sleep here? >> > > I can add the quote to the reference manual while applying. I'll send a V3 with a comment shortly.