From: Reinette Chatre <reinette.chatre@intel.com>
To: Thomas Gleixner <tglx@linutronix.de>,
LKML <linux-kernel@vger.kernel.org>
Cc: <x86@kernel.org>, Joerg Roedel <joro@8bytes.org>,
Will Deacon <will@kernel.org>, <linux-pci@vger.kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
"Marc Zyngier" <maz@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jason Gunthorpe <jgg@mellanox.com>,
Dave Jiang <dave.jiang@intel.com>,
"Alex Williamson" <alex.williamson@redhat.com>,
Kevin Tian <kevin.tian@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Logan Gunthorpe <logang@deltatee.com>,
Ashok Raj <ashok.raj@intel.com>, Jon Mason <jdmason@kudzu.us>,
Allen Hubbe <allenbh@gmail.com>,
"Ahmed S. Darwish" <darwi@linutronix.de>
Subject: Re: [patch 33/33] irqchip: Add IDXD Interrupt Message Store driver
Date: Fri, 2 Dec 2022 09:55:58 -0800 [thread overview]
Message-ID: <4a15c569-0545-20ac-e74c-ae17f7eb067d@intel.com> (raw)
In-Reply-To: <20221111135207.141746268@linutronix.de>
Hi Thomas,
On 11/11/2022 5:59 AM, Thomas Gleixner wrote:
> Provide a driver for the Intel IDXD IMS implementation. The implementation
> uses a large message store array in device memory.
>
> The IMS domain implementation is minimal and just provides the required
> irq_chip callbacks and one domain callback which prepares the MSI
> descriptor which is allocated by the core for easy usage in the irq_chip
> callbacks.
>
> The necessary iobase is stored in the irqdomain and the PASID which is
> required for operation is handed in via msi_dev_cookie in the allocation
> function.
The use of PASID is optional for dedicated workqueues. Could this be
supported to let the irqchip support all scenarios? Since the cookie is
always provided I was wondering if an invalid PASID can be used to let
the driver disable PASID? Please see the delta snippet below in which I
primarily made such a change, but added a few more changes for
consideration.
Summary of changes:
* Use provided invalid PASID to disable PASID for the interrupt.
* Use bitmask to ensure that the cookie only contains a valid PASID.
* Modify header comment to fix typo.
* Modify header comment to reflect driver usage of macro.
With the first change I am able to test IMS on the host using devmsi-v2-part3
of the development branch. I did try to update to the most recent development
to confirm all is well but version devmsi-v3.1-part3 behaves differently
in that pci_ims_alloc_irq() returns successfully but the returned
virq is 0. This triggers a problem when request_threaded_irq() runs and
reports:
genirq: Flags mismatch irq 0. 00000000 (idxd-portal) vs. 00015a00 (timer)
Thank you very much
Reinette
---
drivers/irqchip/irq-pci-intel-idxd.c | 20 ++++++++++++++------
include/linux/irqchip/irq-pci-intel-idxd.h | 4 ++--
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-pci-intel-idxd.c b/drivers/irqchip/irq-pci-intel-idxd.c
index d33c32787ad5..1b49c884bd85 100644
--- a/drivers/irqchip/irq-pci-intel-idxd.c
+++ b/drivers/irqchip/irq-pci-intel-idxd.c
@@ -4,6 +4,7 @@
* interrupt message store (IMS).
*/
#include <linux/device.h>
+#include <linux/ioasid.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/msi.h>
@@ -33,6 +34,8 @@ struct ims_slot {
#define CTRL_PASID_ENABLE BIT(3)
/* Position of PASID.LSB in the control word */
#define CTRL_PASID_SHIFT 12
+/* Valid PASID is 20 bits */
+#define CTRL_PASID_VALID GENMASK(19, 0)
static inline void iowrite32_and_flush(u32 value, void __iomem *addr)
{
@@ -93,12 +96,17 @@ static void idxd_prepare_desc(struct irq_domain *domain, msi_alloc_info_t *arg,
/* Mask the interrupt for paranoia sake */
iowrite32_and_flush(CTRL_VECTOR_MASKBIT, &slot->ctrl);
- /*
- * The caller provided PASID. Shift it to the proper position
- * and set the PASID enable bit.
- */
- desc->data.icookie.value <<= CTRL_PASID_SHIFT;
- desc->data.icookie.value |= CTRL_PASID_ENABLE;
+ if (pasid_valid((ioasid_t)desc->data.icookie.value)) {
+ /*
+ * The caller provided PASID. Shift it to the proper position
+ * and set the PASID enable bit.
+ */
+ desc->data.icookie.value &= CTRL_PASID_VALID;
+ desc->data.icookie.value <<= CTRL_PASID_SHIFT;
+ desc->data.icookie.value |= CTRL_PASID_ENABLE;
+ } else {
+ desc->data.icookie.value = 0;
+ }
arg->hwirq = desc->msi_index;
}
diff --git a/include/linux/irqchip/irq-pci-intel-idxd.h b/include/linux/irqchip/irq-pci-intel-idxd.h
index d62ef5b3285c..48c73bffbb5d 100644
--- a/include/linux/irqchip/irq-pci-intel-idxd.h
+++ b/include/linux/irqchip/irq-pci-intel-idxd.h
@@ -9,8 +9,8 @@
#include <linux/types.h>
/*
- * Conveniance macro to wrap the PASID for interrupt allocation
- * via pci_ims_alloc_irq(pdev, INTEL_IDXD_DEV_COOKIE(pasid))
+ * Convenience macro to wrap the PASID for interrupt allocation
+ * via pci_ims_alloc_irq(pdev, &INTEL_IDXD_DEV_COOKIE(pasid))
*/
#define INTEL_IDXD_DEV_COOKIE(pasid) (union msi_instance_cookie) { .value = (pasid), }
---
next prev parent reply other threads:[~2022-12-02 17:56 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 13:58 [patch 00/33] genirq, PCI/MSI: Support for per device MSI and PCI/IMS - Part 3 implementation Thomas Gleixner
2022-11-11 13:58 ` [patch 01/33] genirq/msi: Rearrange MSI domain flags Thomas Gleixner
2022-11-16 18:41 ` Jason Gunthorpe
2022-11-11 13:58 ` [patch 02/33] genirq/msi: Provide struct msi_parent_ops Thomas Gleixner
2022-11-16 18:57 ` Jason Gunthorpe
2022-11-17 15:58 ` Thomas Gleixner
2022-11-18 13:52 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 03/33] genirq/msi: Provide data structs for per device domains Thomas Gleixner
2022-11-11 13:58 ` [patch 04/33] genirq/msi: Add size info to struct msi_domain_info Thomas Gleixner
2022-11-11 13:58 ` [patch 05/33] genirq/msi: Split msi_create_irq_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 06/33] genirq/irqdomain: Add irq_domain::dev for per device MSI domains Thomas Gleixner
2022-11-11 13:58 ` [patch 07/33] genirq/msi: Provide msi_create/free_device_irq_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 08/33] genirq/msi: Provide msi_match_device_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 09/33] genirq/msi: Add range checking to msi_insert_desc() Thomas Gleixner
2022-11-11 13:58 ` [patch 10/33] PCI/MSI: Split __pci_write_msi_msg() Thomas Gleixner
2022-11-16 20:10 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 11/33] genirq/msi: Provide BUS_DEVICE_PCI_MSI[X] Thomas Gleixner
2022-11-11 13:58 ` [patch 12/33] PCI/MSI: Add support for per device MSI[X] domains Thomas Gleixner
2022-11-16 19:13 ` Jason Gunthorpe
2022-11-16 22:38 ` Thomas Gleixner
2022-11-17 0:22 ` Jason Gunthorpe
2022-11-17 8:45 ` Thomas Gleixner
2022-11-16 20:22 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 13/33] x86/apic/vector: Provide MSI parent domain Thomas Gleixner
2022-11-16 19:18 ` Jason Gunthorpe
2022-11-17 20:06 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 14/33] PCI/MSI: Remove unused pci_dev_has_special_msi_domain() Thomas Gleixner
2022-11-16 20:13 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 15/33] iommu/vt-d: Switch to MSI parent domains Thomas Gleixner
2022-11-11 13:58 ` [patch 16/33] iommu/amd: Switch to MSI base domains Thomas Gleixner
2022-11-11 13:58 ` [patch 17/33] x86/apic/msi: Remove arch_create_remap_msi_irq_domain() Thomas Gleixner
2022-11-11 13:58 ` [patch 18/33] genirq/msi: Provide struct msi_map Thomas Gleixner
2022-11-11 13:58 ` [patch 19/33] genirq/msi: Provide msi_desc::msi_data Thomas Gleixner
2022-11-16 19:28 ` Jason Gunthorpe
2022-11-17 8:48 ` Thomas Gleixner
2022-11-17 13:33 ` Jason Gunthorpe
2022-11-18 22:08 ` Thomas Gleixner
2022-11-21 17:20 ` Jason Gunthorpe
2022-11-21 19:40 ` Thomas Gleixner
2022-11-22 1:52 ` Jason Gunthorpe
2022-11-22 20:49 ` Thomas Gleixner
2022-11-23 16:58 ` Jason Gunthorpe
2022-11-23 18:38 ` Thomas Gleixner
2022-12-01 12:24 ` Thomas Gleixner
2022-12-02 0:35 ` Jason Gunthorpe
2022-12-02 2:14 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 20/33] genirq/msi: Provide msi_domain_ops::prepare_desc() Thomas Gleixner
2022-11-11 13:58 ` [patch 21/33] genirq/msi: Provide msi_domain_alloc_irq_at() Thomas Gleixner
2022-11-16 19:36 ` Jason Gunthorpe
2022-11-17 9:40 ` Thomas Gleixner
2022-11-17 23:33 ` Reinette Chatre
2022-11-18 0:58 ` Thomas Gleixner
2022-11-18 9:15 ` Thomas Gleixner
2022-11-18 11:05 ` Thomas Gleixner
2022-11-18 18:18 ` Reinette Chatre
2022-11-18 22:31 ` Thomas Gleixner
2022-11-18 22:59 ` Reinette Chatre
2022-11-19 0:19 ` Reinette Chatre
2022-11-11 13:58 ` [patch 22/33] genirq/msi: Provide MSI_FLAG_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-16 19:36 ` Jason Gunthorpe
2022-11-11 13:58 ` [patch 23/33] PCI/MSI: Split MSIX descriptor setup Thomas Gleixner
2022-11-16 20:13 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 24/33] PCI/MSI: Provide prepare_desc() MSI domain op Thomas Gleixner
2022-11-16 19:40 ` Jason Gunthorpe
2022-11-16 20:26 ` Bjorn Helgaas
2022-11-16 22:42 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 25/33] PCI/MSI: Provide post-enable dynamic allocation interfaces for MSI-X Thomas Gleixner
2022-11-16 20:19 ` Bjorn Helgaas
2022-11-16 22:43 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 26/33] x86/apic/msi: Enable MSI_FLAG_PCI_MSIX_ALLOC_DYN Thomas Gleixner
2022-11-11 13:58 ` [patch 27/33] genirq/msi: Provide constants for PCI/IMS support Thomas Gleixner
2022-11-16 19:54 ` Jason Gunthorpe
2022-11-17 9:46 ` Thomas Gleixner
2022-11-11 13:58 ` [patch 28/33] PCI/MSI: Provide IMS (Interrupt Message Store) support Thomas Gleixner
2022-11-16 20:17 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 29/33] PCI/MSI: Provide pci_ims_alloc/free_irq() Thomas Gleixner
2022-11-16 20:14 ` Bjorn Helgaas
2022-11-11 13:58 ` [patch 30/33] x86/apic/msi: Enable PCI/IMS Thomas Gleixner
2022-11-11 13:59 ` [patch 31/33] iommu/vt-d: " Thomas Gleixner
2022-11-11 13:59 ` [patch 32/33] iommu/amd: " Thomas Gleixner
2022-11-11 13:59 ` [patch 33/33] irqchip: Add IDXD Interrupt Message Store driver Thomas Gleixner
2022-12-02 17:55 ` Reinette Chatre [this message]
2022-12-02 19:51 ` Thomas Gleixner
2022-12-02 21:16 ` Reinette Chatre
2022-12-05 15:20 ` Thomas Gleixner
2022-12-05 17:19 ` Reinette Chatre
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