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Mon, 31 Aug 2026 17:34:03 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v3 02/13] iommu/arm-smmu-v3: Add Q_POS() macro Date: Mon, 31 Aug 2026 17:33:27 -0700 Message-ID: <4aede16c4e2b68b280793a927fe32b6bd8ef457a.1788222485.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000026C5:EE_|IA0PR12MB8373:EE_ X-MS-Office365-Filtering-Correlation-Id: 8a768b64-b617-458f-3805-08df07c0c370 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|23010399003|376014|7416014|10067099003|11063799006|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: /MG4QMmgKfsEfJWkP7xzlzOOGRnQBGwI/GKwIkOhuyjRUsyF4V4iQDorQxvQWG7GcVPrm5wG2K44TzJuBXJPXj5yqCp5kJEw0TUXP4FQ8c3ww5b58xP190e1N6sKcrV3LluVCIUeAh7kRdbmMOxhbgurtok0848DyMPas/xM5n7wHIJ8duAHcBt8GIDpRS7KKpaV3MrfLzRh0Zg0fSPI0IgUo9HdGp0KXpex4WUsy150t8OrToAjlDVB3WupT+2ArwJwgnK3PJTku6I1n5Is/jOvUJXs4Bcs402CNHjHk7BwI1aJ8hJQrHr4Fq+5/FBKKp9sSjDGmgFpIDoYQa+sRhqIHFg/v6tlJhdslQJ6gQWhTZhT11MZ7kHxK9DueYVAQxScUbOiwnnuCAdlOfxok2Jh6ZDagJANX/EQdtfATf82OQlFbuCs11P82sQ+JeyTlqTocVTodpP8EUoFlbSoTCrISHWc5qwnKN/pLZnb7F8adzh/Libwa4cFUr7F8hZhCw38ActoLggHWsJKt5CTJMu4mrVk6os8L3+btmc2JazhK9ADtvquE0GX5cUVemR0F7GMJVqhRjmY+T/tHnbNc0j8JIdX48uwMW4Nevy3YlLRiAElaoMNLtohQ3/O+4HW/7VzklKrUvaKDTuI4vX9yEpEQYwhrxdN2l/o/sTy3oQgthEwd9kMxXPBlzsSRX4jm7iRnsP3nyE+Y81OJ/S5hg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(23010399003)(376014)(7416014)(10067099003)(11063799006)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FyIH3mLNppHss1qs+3U36/VYzbSCeELGdW6BVKAC3n9M/Ahj/Iw+UUJ7J6UE8g/snXt9IDSgC1MJ3Awj5krxg1WAC5vr7RrfzLke8Iw9HuWgj0fz0/HhJ2P/kROvc4qEUgDu0m86epwAk02ENyJ6+4LFVU+KtMcGqfFZdycPhFj6+RRaJYGDEbRr7+XQoYDfTf8tAe+k7lNbG7cnfB+XgD/VTTbl4TWAgvachzvt0HhG6qTcW3Hx3IP0iXZ7h4H7MjXRsfRfseoMQEGV/VV8Dcp6IQdZnX6ueSspW5Th4uO685eAIxTWotUb3IlqG0K+zEB+vuIovmE2gdKAbyBP38BTwI+XieKMPZXrtRRWOS09kfrKZCcpBme/F/NIaf6Vq/qD8XfHKsXglMvzMcaqD0hxnQgI2H1ptEjDa4tcFf5Q2Hy1JORLnSGjGVfLUnXE X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2026 00:34:20.2901 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8a768b64-b617-458f-3805-08df07c0c370 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8373 A queue position, the wrap bit combined with the index, is Q_WRP | Q_IDX. It is a (max_n_shift + 1)-bit value that wraps at twice the queue capacity. queue_inc_cons(), queue_sync_cons_ovf(), and queue_inc_prod_n() currently compute such positions by open-coding the two macros at each call site. Add a Q_POS() macro and switch the open-coded sites to it. A subsequent change will apply Q_POS() to a position difference, to count the entries that a queue pointer moved past. No functional change intended. Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 11 +++++------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 5b89bad71c102..de7e4284658a1 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -187,6 +187,8 @@ struct arm_vsmmu; #define Q_IDX(llq, p) ((p) & ((1 << (llq)->max_n_shift) - 1)) #define Q_WRP(llq, p) ((p) & (1 << (llq)->max_n_shift)) +/* A position is Q_WRP | Q_IDX, wrapping at twice the queue capacity */ +#define Q_POS(llq, p) (Q_WRP(llq, p) | Q_IDX(llq, p)) #define Q_OVERFLOW_FLAG (1U << 31) #define Q_OVF(p) ((p) & Q_OVERFLOW_FLAG) #define Q_ENT(q, p) ((q)->base + \ diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 99baa59b39c9d..e00b6c88214f5 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -181,8 +181,8 @@ static void queue_sync_cons_out(struct arm_smmu_queue *q) static void queue_inc_cons(struct arm_smmu_ll_queue *q) { - u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; - q->cons = Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); + u32 cons = Q_POS(q, q->cons) + 1; + q->cons = Q_OVF(q->cons) | Q_POS(q, cons); } static void queue_sync_cons_ovf(struct arm_smmu_queue *q) @@ -192,8 +192,7 @@ static void queue_sync_cons_ovf(struct arm_smmu_queue *q) if (likely(Q_OVF(llq->prod) == Q_OVF(llq->cons))) return; - llq->cons = Q_OVF(llq->prod) | Q_WRP(llq, llq->cons) | - Q_IDX(llq, llq->cons); + llq->cons = Q_OVF(llq->prod) | Q_POS(llq, llq->cons); queue_sync_cons_out(q); } @@ -218,8 +217,8 @@ static int queue_sync_prod_in(struct arm_smmu_queue *q) static u32 queue_inc_prod_n(struct arm_smmu_ll_queue *q, int n) { - u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + n; - return Q_OVF(q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod); + u32 prod = Q_POS(q, q->prod) + n; + return Q_OVF(q->prod) | Q_POS(q, prod); } static void queue_poll_init(struct arm_smmu_device *smmu, -- 2.43.0