From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-da0-f47.google.com ([209.85.210.47]:38479 "EHLO mail-da0-f47.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932863Ab3CHXMI (ORCPT ); Fri, 8 Mar 2013 18:12:08 -0500 Received: by mail-da0-f47.google.com with SMTP id s35so226187dak.6 for ; Fri, 08 Mar 2013 15:12:07 -0800 (PST) Message-ID: <513A7044.1020700@gmail.com> Date: Fri, 08 Mar 2013 17:12:04 -0600 From: Rob Herring MIME-Version: 1.0 To: Thierry Reding CC: Jason Gunthorpe , Thomas Petazzoni , Lior Amsalem , Andrew Lunn , Russell King - ARM Linux , Jason Cooper , Arnd Bergmann , Stephen Warren , linux-pci@vger.kernel.org, Eran Ben-Avi , Nadav Haklai , Maen Suleiman , Shadi Ammouri , Bjorn Helgaas , Gregory Clement , Tawfik Bayouk , Grant Likely , linux-arm-kernel@lists.infradead.org, devicetree-discuss@lists.ozlabs.org Subject: Re: [PATCH 24/32] pci: PCIe driver for Marvell Armada 370/XP systems References: <20130212223511.GB31555@obsidianresearch.com> <20130306105441.4d24033e@skate> <20130306121118.GA17079@avionic-0098.mockup.avionic-design.de> <20130306180946.GA2433@obsidianresearch.com> <20130307080832.GD3451@avionic-0098.mockup.avionic-design.de> <20130307174955.GC20840@obsidianresearch.com> <20130307194830.GA1811@avionic-0098.mockup.avionic-design.de> <20130307200235.GB20695@obsidianresearch.com> <20130307204726.GB1811@avionic-0098.mockup.avionic-design.de> <51392B4D.9040404@gmail.com> <20130308071443.GA5772@avionic-0098.mockup.avionic-design.de> In-Reply-To: <20130308071443.GA5772@avionic-0098.mockup.avionic-design.de> Content-Type: text/plain; charset=ISO-8859-1 Sender: linux-pci-owner@vger.kernel.org List-ID: On 03/08/2013 01:14 AM, Thierry Reding wrote: > On Thu, Mar 07, 2013 at 06:05:33PM -0600, Rob Herring wrote: >> On 03/07/2013 02:47 PM, Thierry Reding wrote: > [...] >>> In a nutshell (since some of the context isn't quoted anymore) the >>> problem that we're trying to solve is that some of the embedded SoCs >>> require per-root-port registers for configuration. The PCI DT >>> specification doesn't make any provisions for this. A few alternatives >>> have been discussed so far: >> >> I'm not sure I follow. This is different than the host controller >> registers? Why would this not just be multiple entries in the reg property? > > Well the register regions are per root-port. On Tegra20 there's 2 of > them, Tegra30 has 3 and if I understand correctly Marvell can have up to > 10 (!). Adding all of them to the reg property of the host controller > could work but it needs some way to match the reg entry to the root port > similar to option 1 below. The compatible property of the PCI host controller can imply what each index of the reg property entries is for. > > Adding a property in the root port nodes seems like a cleaner and more > accurate representation of the hardware to me, but if that's not > acceptable perhaps we need to bite the bullet and add the code to look > the registers up from the parent's reg property. What I don't like is a new property defined to describe mmio addresses. We already have a property for that and it is "reg". But I think I'm still missing something: >>> pci@0,1 { >>> ... >>> reg = <0x00000800 0 0 0 0>; Is this a PCI bus address? >>> regs = <0x80000000 0x00001000>; >>> }; Rob