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Date: Thu, 11 Jul 2013 14:24:36 +0530
From: Kishon Vijay Abraham I <kishon@ti.com>
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To: Jingoo Han <jg1.han@samsung.com>
CC: "'Bjorn Helgaas'" <bhelgaas@google.com>,
	<linux-pci@vger.kernel.org>, <linux-samsung-soc@vger.kernel.org>,
	"'Kukjin Kim'" <kgene.kim@samsung.com>,
	Pratyush Anand <pratyush.anand@st.com>,
	Mohit KUMAR <Mohit.KUMAR@st.com>,
	"'Arnd Bergmann'" <arnd@arndb.de>,
	"'Sean Cross'" <xobs@kosagi.com>,
	"'SRIKANTH TUMKUR SHIVANAND'" <ts.srikanth@samsung.com>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V2] pci: exynos: split into two parts such as Synopsys
 part and Exynos part
References: <001201ce7dfa$716b3370$54419a50$@samsung.com>
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Hi,

On Thursday 11 July 2013 11:19 AM, Jingoo Han wrote:
> Exynos PCIe IP consists of Synopsys specific part and Exynos
> specific part. Only core block is a Synopsys designware part;
> other parts are Exynos specific.
> Also, the Synopsys designware part can be shared with other
> platforms; thus, it can be split two parts such as Synopsys
> designware part and Exynos specific part.
> 
> Signed-off-by: Jingoo Han <jg1.han@samsung.com>
> Cc: Pratyush Anand <pratyush.anand@st.com>
> Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
> ---
.
.
<snip>
.
.
> +
> +/* Exynos PCIe driver does not allow module unload */

Just curious, why is this restriction?

Thanks
Kishon