Re: pcie designware question

[Murali Karicheri <m-karicheri2@ti.com>]

On 12/19/2013 11:21 PM, Mohit KUMAR DCG wrote:
>>> I have reviewed the designware.c code and the glue logic driver
>>> pci-exynos.c and couldn't understand few things.
>>>
>>> 1. Our pcie ss is based on designware core and following addresses are
>>> not listed in our IP's  data manual. Where is defined? It does show
>>> the rest of the offsets defined in  drivers/pci/host/designware.c and
>>>
>>> #define PCIE_ATU_VIEWPORT               0x900
>>> #define PCIE_ATU_REGION_INBOUND         (0x1 << 31)
>>> #define PCIE_ATU_REGION_OUTBOUND        (0x0 << 31)
>>> #define PCIE_ATU_REGION_INDEX1          (0x1 << 0)
>>> #define PCIE_ATU_REGION_INDEX0          (0x0 << 0)
>>> #define PCIE_ATU_CR1                    0x904
>>> #define PCIE_ATU_TYPE_MEM               (0x0 << 0)
>>> #define PCIE_ATU_TYPE_IO                (0x2 << 0)
>>> #define PCIE_ATU_TYPE_CFG0              (0x4 << 0)
>>> #define PCIE_ATU_TYPE_CFG1              (0x5 << 0)
>>> #define PCIE_ATU_CR2                    0x908
>>> #define PCIE_ATU_ENABLE                 (0x1 << 31)
>>> #define PCIE_ATU_BAR_MODE_ENABLE        (0x1 << 30)
>>> #define PCIE_ATU_LOWER_BASE             0x90C
>>> #define PCIE_ATU_UPPER_BASE             0x910
>>> #define PCIE_ATU_LIMIT                  0x914
>>> #define PCIE_ATU_LOWER_TARGET           0x918
>>> #define PCIE_ATU_BUS(x)                 (((x) & 0xff) << 24)
>>> #define PCIE_ATU_DEV(x)                 (((x) & 0x1f) << 19)
>>> #define PCIE_ATU_FUNC(x)                (((x) & 0x7) << 16)
>>> #define PCIE_ATU_UPPER_TARGET           0x91C
> - These are Synopsys specific port logic registers. You can find these registers at offset 0x200
>   under port logic registers section in Synpsys PCIe DM.  There can be minor difference in the name
> convention as it is called 'iATU Viewport Register' in controller version3.70 and 'iATU Index Register'
>   in version 4.11.
> By the way which version of IP manual you are referring?
>
>
Mohit,

I have checked with our hardware team and they confirmed that ATU 
registers are not implemented in our PCIE
SS. So we need to have  a way to disable this in the core driver so 
that  we can handle it in our glue layer driver.
But this will be a regression on the existing driver. How do we handle this?

Murali