From: Murali Karicheri <m-karicheri2@ti.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robherring2@gmail.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Russell King <linux@arm.linux.org.uk>,
Grant Likely <grant.likely@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Mohit Kumar <mohit.kumar@st.com>,
Jingoo Han <jg1.han@samsung.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Pratyush Anand <pratyush.anand@st.com>,
Richard Zhu <r65037@freescale.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Marek Vasut <marex@denx.de>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Randy Dunlap <rdunlap@infradead.org>
Subject: Re: [PATCH v6 4/5] PCI: add PCI controller for keystone PCIe h/w
Date: Fri, 18 Jul 2014 16:15:53 -0400 [thread overview]
Message-ID: <53C98079.4080707@ti.com> (raw)
In-Reply-To: <5467203.eMVRoNeSx1@wuerfel>
On 07/18/2014 03:50 PM, Arnd Bergmann wrote:
> On Friday 18 July 2014 14:31:39 Rob Herring wrote:
>>> +
>>> + Example:
>>> + pcie_msi_intc: msi-interrupt-controller {
>>> + interrupt-controller;
>>> + #interrupt-cells =<1>;
>>> + interrupt-parent =<&gic>;
>>> + interrupts =<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
>>> +<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
>>> +<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
>>> +<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
>>> +<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
>>> +<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
>>> +<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
>>> +<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
>>> + };
>>> +
>>> +pcie_intc: Interrupt controller device node for Legacy irq chip
>>> + interrupt-cells: should be set to 1
>>> + interrupt-parent: Parent interrupt controller phandle
>>> + interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines
>>> +
>>> + Example:
>>> + pcie_intc: legacy-interrupt-controller {
>>> + interrupt-controller;
>>> + #interrupt-cells =<1>;
>>> + interrupt-parent =<&gic>;
>>> + interrupts =<GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
>>> +<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
>>> +<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
>>> +<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
>>> + };
>> This seems wrong. Legacy interrupts should be described with
>> interrupt-map and then PCI child devices have a standard interrupt
>> specifier.
>>
>> I'm not sure about MSIs, but I would think they would have a standard
>> format too.
>>
> IIRC, it's actually the correct way to do this here: the problem is that
> the PCI IRQs are not directly connected to the GIC, but instead there is
> a nested irqchip that has each PCI IRQ routed to it and that requires
> an extra EOI for each interrupt.
>
> The interrupt-map in the PCI host points to this special irqchip rather
> than to the GIC.
Arnd,
Thanks. I agree with Arnd and believe there is no issue here
> Arnd
> --
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next prev parent reply other threads:[~2014-07-18 20:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-07-18 15:14 [PATCH v6 0/5] Add Keystone PCIe controller driver Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 1/5] PCI: designware: add rd[wr]_other_conf API Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 2/5] PCI: designware: refactor MSI code to work with v3.65 dw hardware Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 3/5] PCI: designware: enhance dw_pcie_host_init() to support v3.65 DW hardware Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 4/5] PCI: add PCI controller for keystone PCIe h/w Murali Karicheri
2014-07-18 19:31 ` Rob Herring
2014-07-18 19:50 ` Arnd Bergmann
2014-07-18 20:15 ` Murali Karicheri [this message]
2014-07-22 15:37 ` Rob Herring
2014-07-22 19:00 ` Murali Karicheri
2014-07-18 20:29 ` Murali Karicheri
2014-07-21 1:44 ` Jingoo Han
2014-07-21 16:39 ` Murali Karicheri
2014-07-22 15:41 ` Rob Herring
2014-07-22 18:58 ` Murali Karicheri
2014-07-18 15:14 ` [PATCH v6 5/5] PCI: keystone: Update maintainer information Murali Karicheri
2014-07-18 15:19 ` [PATCH v6 0/5] Add Keystone PCIe controller driver Murali Karicheri
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