From: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@linux.intel.com>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-cxl@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>,
oohall@gmail.com, Lukas Wunner <lukas@wunner.de>,
Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Yazen Ghannam <yazen.ghannam@amd.com>,
Terry Bowman <terry.bowman@amd.com>,
Robert Richter <rrichter@amd.com>
Subject: Re: [PATCH 2/2] cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers
Date: Wed, 19 Jul 2023 13:39:23 -0700 [thread overview]
Message-ID: <53d5eeb3-5a13-3663-57a1-e927c4c369b8@linux.intel.com> (raw)
In-Reply-To: <20230719192313.38591-3-Smita.KoralahalliChannabasappa@amd.com>
On 7/19/23 12:23 PM, Smita Koralahalli wrote:
> According to Section 9.17.2, Table 9-26 of CXL Specification [1], owner
> of AER should also own CXL Protocol Error Management as there is no
> explicit control of CXL Protocol error. And the CXL RAS Cap registers
> reported on Protocol errors should check for AER _OSC rather than CXL
> Memory Error Reporting Control _OSC.
>
> The CXL Memory Error Reporting Control _OSC specifically highlights
> handling Memory Error Logging and Signaling Enhancements. These kinds of
> errors are reported through a device's mailbox and can be managed
> independently from CXL Protocol Errors.
Does it fix any issue? If yes, please include that in the commit log.
Since you are removing some change, maybe it needs Fixes: tag?
>
> [1] Compute Express Link (CXL) Specification, Revision 3.1, Aug 1 2022.
>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
> ---
> drivers/cxl/pci.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 1cb1494c28fe..44a21ab7add5 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>
> static int cxl_pci_ras_unmask(struct pci_dev *pdev)
> {
> - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus);
> struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
> void __iomem *addr;
> u32 orig_val, val, mask;
> @@ -541,9 +540,9 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev)
> return 0;
> }
>
> - /* BIOS has CXL error control */
> - if (!host_bridge->native_cxl_error)
> - return -ENXIO;
> + /* BIOS has PCIe AER error control */
> + if (!pcie_aer_is_native(pdev))
> + return 0;
>
> rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);
> if (rc)
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
next prev parent reply other threads:[~2023-07-19 20:39 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-19 19:23 [PATCH 0/2] PCI, AER, CXL: Fix appropriate _OSC check for CXL RAS Cap Smita Koralahalli
2023-07-19 19:23 ` [PATCH 1/2] PCI, AER: Export and make pcie_aer_is_native() global Smita Koralahalli
2023-07-19 20:36 ` Bjorn Helgaas
2023-07-19 22:06 ` Smita Koralahalli
2023-07-19 20:40 ` Sathyanarayanan Kuppuswamy
2023-07-19 19:23 ` [PATCH 2/2] cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers Smita Koralahalli
2023-07-19 20:39 ` Sathyanarayanan Kuppuswamy [this message]
2023-07-19 22:30 ` Smita Koralahalli
2023-07-20 13:07 ` Robert Richter
2023-07-20 18:31 ` Smita Koralahalli
2023-07-21 13:49 ` Robert Richter
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