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([2a01:e0a:3d9:2080:6f64:6b96:cac5:a35f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47d870e80bbsm67752485e9.5.2026.01.09.05.10.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 09 Jan 2026 05:10:50 -0800 (PST) Message-ID: <53f0c45f-7f5c-4abd-af84-cbb82d509872@linaro.org> Date: Fri, 9 Jan 2026 14:10:49 +0100 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH 1/5] phy: qcom: qmp-pcie: Skip PHY reset if already up To: Dmitry Baryshkov , Krishna Chaitanya Chundru Cc: Vinod Koul , Philipp Zabel , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20260109-link_retain-v1-0-7e6782230f4b@oss.qualcomm.com> <20260109-link_retain-v1-1-7e6782230f4b@oss.qualcomm.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 1/9/26 14:08, Dmitry Baryshkov wrote: > On Fri, Jan 09, 2026 at 12:51:06PM +0530, Krishna Chaitanya Chundru wrote: >> If the bootloader has already powered up the PCIe PHY, doing a full >> reset and waiting for it to come up again slows down boot time. > > How big is the delay caused by it? > >> >> Add a check for PHY status and skip the reset steps when the PHY is >> already active. In this case, only enable the required resources during >> power-on. This works alongside the existing logic that skips the init >> sequence. > > Can we end up in a state where the bootloader has mis-setup the link? Or > the link going bad because of any glitch during the bootup? Good question, can we add a module parameter to force a full reset of the PHY in case the bootloader is buggy ? > >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 28 ++++++++++++++++++---------- >> 1 file changed, 18 insertions(+), 10 deletions(-) >> >> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> index 86b1b7e2da86a8675e3e48e90b782afb21cafd77..c93e613cf80b2612f0f225fa2125f78dbec1a33f 100644 >> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c >> @@ -3153,6 +3153,7 @@ struct qmp_pcie { >> const struct qmp_phy_cfg *cfg; >> bool tcsr_4ln_config; >> bool skip_init; >> + bool skip_reset; >> >> void __iomem *serdes; >> void __iomem *pcs; >> @@ -4537,6 +4538,9 @@ static int qmp_pcie_init(struct phy *phy) >> qphy_checkbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START) && >> qphy_checkbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl); >> >> + qmp->skip_reset = qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY_PCS_STATUS], > > It is definitely not a long-term state, there is no need to store it in > qmp_pcie struct. > >> + cfg->phy_status); >> + >> if (!qmp->skip_init && !cfg->tbls.serdes_num) { >> dev_err(qmp->dev, "Init sequence not available\n"); >> return -ENODATA; >> @@ -4560,13 +4564,15 @@ static int qmp_pcie_init(struct phy *phy) >> } >> } >> >> - ret = reset_control_assert(qmp->nocsr_reset); >> - if (ret) { >> - dev_err(qmp->dev, "no-csr reset assert failed\n"); >> - goto err_assert_reset; >> - } >> + if (!qmp->skip_reset) { >> + ret = reset_control_assert(qmp->nocsr_reset); >> + if (ret) { >> + dev_err(qmp->dev, "no-csr reset assert failed\n"); >> + goto err_assert_reset; >> + } >> >> - usleep_range(200, 300); >> + usleep_range(200, 300); >> + } >> >> if (!qmp->skip_init) { >> ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); >> @@ -4641,10 +4647,12 @@ static int qmp_pcie_power_on(struct phy *phy) >> if (ret) >> return ret; >> >> - ret = reset_control_deassert(qmp->nocsr_reset); >> - if (ret) { >> - dev_err(qmp->dev, "no-csr reset deassert failed\n"); >> - goto err_disable_pipe_clk; >> + if (!qmp->skip_reset) { >> + ret = reset_control_deassert(qmp->nocsr_reset); >> + if (ret) { >> + dev_err(qmp->dev, "no-csr reset deassert failed\n"); >> + goto err_disable_pipe_clk; >> + } >> } >> >> if (qmp->skip_init) >> >> -- >> 2.34.1 >> >