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From: Rob Herring <robh@kernel.org>
To: Zhou Wang <wangzhou1@hisilicon.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	jingoohan1@gmail.com, pratyush.anand@gmail.com,
	Arnd Bergmann <arnd@arndb.de>,
	linux@arm.linux.org.uk, thomas.petazzoni@free-electrons.com,
	gabriele.paoloni@huawei.com, lorenzo.pieralisi@arm.com,
	james.morse@arm.com, Liviu.Dudau@arm.com, jason@lakedaemon.net,
	gabriel.fernandez@linaro.org, Minghuan.Lian@freescale.com,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	devicetree@vger.kernel.org, zhangjukuo@huawei.com,
	qiuzhenfa@hisilicon.com, liudongdong3@huawei.com,
	qiujiang@huawei.com, xuwei5@hisilicon.com,
	liguozhu@hisilicon.com
Subject: Re: [PATCH v9 5/6] Documentation: DT: Add HiSilicon PCIe host binding
Date: Tue, 15 Sep 2015 14:43:53 -0500	[thread overview]
Message-ID: <55F874F9.1060804@kernel.org> (raw)
In-Reply-To: <1442321361-174300-6-git-send-email-wangzhou1@hisilicon.com>

On 09/15/2015 07:49 AM, Zhou Wang wrote:
> This patch adds related DTS binding document for HiSilicon PCIe host driver.
> 
> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
> ---
>  .../devicetree/bindings/pci/hisilicon-pcie.txt     | 46 ++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> 
> diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> new file mode 100644
> index 0000000..2afc9d1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt
> @@ -0,0 +1,46 @@
> +HiSilicon PCIe host bridge DT description
> +
> +HiSilicon PCIe host controller is based on Designware PCI core.
> +It shares common functions with PCIe Designware core driver and inherits
> +common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pci.txt.
> +
> +Additional properties are described here:
> +
> +Required properties:
> +- compatible: Should contain "hisilicon,hip05-pcie".
> +- reg: Should contain rc_dbi, subctrl, config registers location and length.
> +- reg-names: Must include the following entries:
> +  "rc_dbi": controller configuration registers;
> +  "subctrl": whole PCIe hosts configuration registers;
> +  "config": PCIe configuration space registers.
> +- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
> +- port-id: Should be 0, 1, 2 or 3.

What is port-id for? Use of instance indexes need to have good reason.

Rob


  reply	other threads:[~2015-09-15 19:43 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-09-15 12:49 [PATCH v9 0/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 Zhou Wang
2015-09-15 12:49 ` [PATCH v9 1/6] PCI: designware: move calculation of bus addresses to DRA7xx Zhou Wang
2015-09-15 12:49 ` [PATCH v9 2/6] ARM/PCI: remove align_resource in pci_sys_data Zhou Wang
2015-09-15 12:49 ` [PATCH v9 3/6] PCI: designware: Add ARM64 support Zhou Wang
2015-09-22  2:52   ` Zhou Wang
2015-09-22 17:05     ` Pratyush Anand
2015-09-23  3:25       ` Zhou Wang
2015-09-15 12:49 ` [PATCH v9 4/6] PCI: hisi: Add PCIe host support for HiSilicon SoC Hip05 Zhou Wang
2015-09-15 12:49 ` [PATCH v9 5/6] Documentation: DT: Add HiSilicon PCIe host binding Zhou Wang
2015-09-15 19:43   ` Rob Herring [this message]
2015-09-16  1:14     ` Zhou Wang
2015-09-16  2:17       ` Rob Herring
2015-09-16  3:24         ` Zhou Wang
2015-09-15 12:49 ` [PATCH v9 6/6] MAINTAINERS: Add pcie-hisi maintainer Zhou Wang

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