From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ob0-f173.google.com ([209.85.214.173]:33578 "EHLO mail-ob0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751945AbbIOTn4 (ORCPT ); Tue, 15 Sep 2015 15:43:56 -0400 Subject: Re: [PATCH v9 5/6] Documentation: DT: Add HiSilicon PCIe host binding To: Zhou Wang References: <1442321361-174300-1-git-send-email-wangzhou1@hisilicon.com> <1442321361-174300-6-git-send-email-wangzhou1@hisilicon.com> Cc: Bjorn Helgaas , jingoohan1@gmail.com, pratyush.anand@gmail.com, Arnd Bergmann , linux@arm.linux.org.uk, thomas.petazzoni@free-electrons.com, gabriele.paoloni@huawei.com, lorenzo.pieralisi@arm.com, james.morse@arm.com, Liviu.Dudau@arm.com, jason@lakedaemon.net, gabriel.fernandez@linaro.org, Minghuan.Lian@freescale.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, zhangjukuo@huawei.com, qiuzhenfa@hisilicon.com, liudongdong3@huawei.com, qiujiang@huawei.com, xuwei5@hisilicon.com, liguozhu@hisilicon.com From: Rob Herring Message-ID: <55F874F9.1060804@kernel.org> Date: Tue, 15 Sep 2015 14:43:53 -0500 MIME-Version: 1.0 In-Reply-To: <1442321361-174300-6-git-send-email-wangzhou1@hisilicon.com> Content-Type: text/plain; charset=windows-1252 Sender: linux-pci-owner@vger.kernel.org List-ID: On 09/15/2015 07:49 AM, Zhou Wang wrote: > This patch adds related DTS binding document for HiSilicon PCIe host driver. > > Signed-off-by: Zhou Wang > --- > .../devicetree/bindings/pci/hisilicon-pcie.txt | 46 ++++++++++++++++++++++ > 1 file changed, 46 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/hisilicon-pcie.txt > > diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt > new file mode 100644 > index 0000000..2afc9d1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt > @@ -0,0 +1,46 @@ > +HiSilicon PCIe host bridge DT description > + > +HiSilicon PCIe host controller is based on Designware PCI core. > +It shares common functions with PCIe Designware core driver and inherits > +common properties defined in > +Documentation/devicetree/bindings/pci/designware-pci.txt. > + > +Additional properties are described here: > + > +Required properties: > +- compatible: Should contain "hisilicon,hip05-pcie". > +- reg: Should contain rc_dbi, subctrl, config registers location and length. > +- reg-names: Must include the following entries: > + "rc_dbi": controller configuration registers; > + "subctrl": whole PCIe hosts configuration registers; > + "config": PCIe configuration space registers. > +- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts. > +- port-id: Should be 0, 1, 2 or 3. What is port-id for? Use of instance indexes need to have good reason. Rob