* [PATCH v2] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK
@ 2015-08-26 3:17 Zhou Wang
2015-08-26 5:00 ` Jingoo Han
2015-09-15 16:50 ` Bjorn Helgaas
0 siblings, 2 replies; 4+ messages in thread
From: Zhou Wang @ 2015-08-26 3:17 UTC (permalink / raw)
To: jingoohan1, pratyush.anand, gabriele.paoloni
Cc: linux-pci, qiuzhenfa, zhangjukuo, liudongdong3, qiujiang, xuwei5,
liguozhu, Zhou Wang
The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8. Here change
this mask to proper value.
In IP v4.2, bits [16:8] are defined for NUM_OF_LANES. But in IP v4.4, bits[12:8]
are defined for NUM_OF_LANES, bits [16:13] are for other usages(bit 16 is
AUTO_LANE_FLIP_CTRL_EN, bits [15:13] are PRE_DET_LANE).
As there is no conflict about NUM_OF_LANES between v4.2 and v4.4, this patch
change above mask value to avoid future problem.
Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
---
drivers/pci/host/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 69486be..eb549b9 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -35,7 +35,7 @@
#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
-#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
+#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
--
1.9.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK
2015-08-26 3:17 [PATCH v2] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK Zhou Wang
@ 2015-08-26 5:00 ` Jingoo Han
2015-09-15 16:50 ` Bjorn Helgaas
1 sibling, 0 replies; 4+ messages in thread
From: Jingoo Han @ 2015-08-26 5:00 UTC (permalink / raw)
To: Zhou Wang
Cc: <pratyush.anand@gmail.com>,
<gabriele.paoloni@huawei.com>,
<linux-pci@vger.kernel.org>,
<qiuzhenfa@hisilicon.com>, <zhangjukuo@huawei.com>,
<liudongdong3@huawei.com>, <qiujiang@huawei.com>,
<xuwei5@hisilicon.com>, <liguozhu@hisilicon.com>,
jingoohan1
On 2015. 8. 26., at PM 12:17, Zhou Wang <wangzhou1@hisilicon.com> wrote:
>
> The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8. Here change
> this mask to proper value.
>
> In IP v4.2, bits [16:8] are defined for NUM_OF_LANES. But in IP v4.4, bits[12:8]
> are defined for NUM_OF_LANES, bits [16:13] are for other usages(bit 16 is
> AUTO_LANE_FLIP_CTRL_EN, bits [15:13] are PRE_DET_LANE).
>
> As there is no conflict about NUM_OF_LANES between v4.2 and v4.4, this patch
> change above mask value to avoid future problem.
>
> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Best regards,
Jingoo Han
> ---
> drivers/pci/host/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 69486be..eb549b9 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -35,7 +35,7 @@
>
> #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
> #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
> -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
> +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
> #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
> #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
> #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK
2015-08-26 3:17 [PATCH v2] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK Zhou Wang
2015-08-26 5:00 ` Jingoo Han
@ 2015-09-15 16:50 ` Bjorn Helgaas
2015-09-16 1:23 ` Zhou Wang
1 sibling, 1 reply; 4+ messages in thread
From: Bjorn Helgaas @ 2015-09-15 16:50 UTC (permalink / raw)
To: Zhou Wang
Cc: jingoohan1, pratyush.anand, gabriele.paoloni, linux-pci,
qiuzhenfa, zhangjukuo, liudongdong3, qiujiang, xuwei5, liguozhu
On Wed, Aug 26, 2015 at 11:17:34AM +0800, Zhou Wang wrote:
> The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8. Here change
> this mask to proper value.
>
> In IP v4.2, bits [16:8] are defined for NUM_OF_LANES. But in IP v4.4, bits[12:8]
> are defined for NUM_OF_LANES, bits [16:13] are for other usages(bit 16 is
> AUTO_LANE_FLIP_CTRL_EN, bits [15:13] are PRE_DET_LANE).
>
> As there is no conflict about NUM_OF_LANES between v4.2 and v4.4, this patch
> change above mask value to avoid future problem.
>
> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Applied with Jingoo's ack to pci/host-designware for v4.4, thanks!
> ---
> drivers/pci/host/pcie-designware.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 69486be..eb549b9 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -35,7 +35,7 @@
>
> #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
> #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
> -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
> +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
> #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
> #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
> #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK
2015-09-15 16:50 ` Bjorn Helgaas
@ 2015-09-16 1:23 ` Zhou Wang
0 siblings, 0 replies; 4+ messages in thread
From: Zhou Wang @ 2015-09-16 1:23 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: jingoohan1, pratyush.anand, gabriele.paoloni, linux-pci,
qiuzhenfa, zhangjukuo, liudongdong3, qiujiang, xuwei5, liguozhu
On 2015/9/16 0:50, Bjorn Helgaas wrote:
> On Wed, Aug 26, 2015 at 11:17:34AM +0800, Zhou Wang wrote:
>> The value under PORT_LOGIC_LINK_WIDTH_MASK is 0x1, 0x2, 0x4, 0x8. Here change
>> this mask to proper value.
>>
>> In IP v4.2, bits [16:8] are defined for NUM_OF_LANES. But in IP v4.4, bits[12:8]
>> are defined for NUM_OF_LANES, bits [16:13] are for other usages(bit 16 is
>> AUTO_LANE_FLIP_CTRL_EN, bits [15:13] are PRE_DET_LANE).
>>
>> As there is no conflict about NUM_OF_LANES between v4.2 and v4.4, this patch
>> change above mask value to avoid future problem.
>>
>> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
>
> Applied with Jingoo's ack to pci/host-designware for v4.4, thanks!
>
Thanks for applying,
Zhou
>> ---
>> drivers/pci/host/pcie-designware.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
>> index 69486be..eb549b9 100644
>> --- a/drivers/pci/host/pcie-designware.c
>> +++ b/drivers/pci/host/pcie-designware.c
>> @@ -35,7 +35,7 @@
>>
>> #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
>> #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
>> -#define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
>> +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
>> #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
>> #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
>> #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
>> --
>> 1.9.1
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
> .
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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2015-08-26 3:17 [PATCH v2] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK Zhou Wang
2015-08-26 5:00 ` Jingoo Han
2015-09-15 16:50 ` Bjorn Helgaas
2015-09-16 1:23 ` Zhou Wang
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