From: Florian Fainelli <f.fainelli@gmail.com>
To: Paul Burton <paul.burton@imgtec.com>, linux-mips@linux-mips.org
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>,
"Michal Simek" <michal.simek@xilinx.com>,
"Jiang Liu" <jiang.liu@linux.intel.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-pci@vger.kernel.org,
"Russell Joyce" <russell.joyce@york.ac.uk>,
"Arnd Bergmann" <arnd@arndb.de>,
linux-kernel@vger.kernel.org,
"Thomas Gleixner" <tglx@linutronix.de>,
"Jingoo Han" <jingoohan1@gmail.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 20/28] net: pch_gbe: clear interrupt FIFO during probe
Date: Mon, 30 Nov 2015 17:48:44 -0800 [thread overview]
Message-ID: <565CFC7C.101@gmail.com> (raw)
In-Reply-To: <1448900513-20856-21-git-send-email-paul.burton@imgtec.com>
On 30/11/15 08:21, Paul Burton wrote:
> xilinx_pcie_init_port clears the pending interrupts in the interrupt
> decode register, but does not clear the interrupt FIFO. This would lead
> to spurious interrupts if any were present in the FIFO at probe time.
> Clear the interrupt FIFO prior to the interrupt decode register in order
> to start with a clean slate as expected.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Seems like the subject should be "PCI: xilinx: ..." to be consistent
with the changes you are making to this driver earlier in the series?
--
Florian
prev parent reply other threads:[~2015-12-01 1:48 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1448900513-20856-1-git-send-email-paul.burton@imgtec.com>
2015-11-30 16:21 ` [PATCH 05/28] PCI: xilinx: keep references to both IRQ domains Paul Burton
2015-12-04 18:17 ` Bjorn Helgaas
2015-11-30 16:21 ` [PATCH 06/28] PCI: xilinx: unify INTx & MSI interrupt FIFO decode Paul Burton
2015-11-30 16:21 ` [PATCH 07/28] PCI: xilinx: always clear interrupt decode register Paul Burton
2015-11-30 16:21 ` [PATCH 08/28] PCI: xilinx: fix INTX irq dispatch Paul Burton
2015-11-30 16:21 ` [PATCH 09/28] PCI: xilinx: allow build on MIPS platforms Paul Burton
2015-11-30 16:21 ` [PATCH 20/28] net: pch_gbe: clear interrupt FIFO during probe Paul Burton
2015-12-01 1:48 ` Florian Fainelli [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=565CFC7C.101@gmail.com \
--to=f.fainelli@gmail.com \
--cc=arnd@arndb.de \
--cc=bhelgaas@google.com \
--cc=jiang.liu@linux.intel.com \
--cc=jingoohan1@gmail.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=michal.simek@xilinx.com \
--cc=paul.burton@imgtec.com \
--cc=robh@kernel.org \
--cc=russell.joyce@york.ac.uk \
--cc=soren.brinkmann@xilinx.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).