[PATCH V4 0/5] PCIe Xilinx generic driver for Microblaze and

[PATCH V4 0/5] PCIe Xilinx generic driver for Microblaze and

[Bharat Kumar Gogada]

This patch series does modifications to pcie-xilinx.c, to support common
driver on both Zynq and Microblaze architectures.
Microblaze pci-common.c has been modified to support generic driver.

Bharat Kumar Gogada (5):
  PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function
  PCI: xilinx: Removing struct hw_pci structure.
  PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both
     Zynq and Microblaze
  PCI: xilinx: Updating Zynq PCI binding documentation with 
    Microblaze node.
  Microblaze: Modifying microblaze PCI subsytem to support  generic
    Xilinx  AXI PCIe Host Bridge IP driver

 .../devicetree/bindings/pci/xilinx-pcie.txt        |  32 +++-
 arch/microblaze/Kconfig                            |   3 +
 arch/microblaze/pci/pci-common.c                   |  56 ++----
 drivers/pci/host/Kconfig                           |   2 +-
 drivers/pci/host/pcie-xilinx.c                     | 191 +++------------------
 5 files changed, 66 insertions(+), 218 deletions(-)

-- 
2.1.1

[PATCH V4 1/5] PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function

[Bharat Kumar Gogada]

Removing xilinx_pcie_parse_and_add_res function replacing with
of_pci_get_host_bridge_resources API.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
Changes:
Removing xilinx_pcie_parse_and_add_res function and replacing it
with of_pci_get_host_bridge_resources kernel API which does the same.
---
 drivers/pci/host/pcie-xilinx.c | 107 ++---------------------------------------
 1 file changed, 5 insertions(+), 102 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 3c7a0d5..627878d 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -94,9 +94,6 @@
 /* Number of MSI IRQs */
 #define XILINX_NUM_MSI_IRQS		128
 
-/* Number of Memory Resources */
-#define XILINX_MAX_NUM_RESOURCES	3
-
 /**
  * struct xilinx_pcie_port - PCIe port information
  * @reg_base: IO Mapped Register Base
@@ -105,7 +102,6 @@
  * @root_busno: Root Bus number
  * @dev: Device pointer
  * @irq_domain: IRQ domain pointer
- * @bus_range: Bus range
  * @resources: Bus Resources
  */
 struct xilinx_pcie_port {
@@ -659,97 +655,6 @@ static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 }
 
 /**
- * xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
- * @port: PCIe port information
- *
- * Return: '0' on success and error value on failure
- */
-static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
-{
-	struct device *dev = port->dev;
-	struct device_node *node = dev->of_node;
-	struct resource *mem;
-	resource_size_t offset;
-	struct of_pci_range_parser parser;
-	struct of_pci_range range;
-	struct resource_entry *win;
-	int err = 0, mem_resno = 0;
-
-	/* Get the ranges */
-	if (of_pci_range_parser_init(&parser, node)) {
-		dev_err(dev, "missing \"ranges\" property\n");
-		return -EINVAL;
-	}
-
-	/* Parse the ranges and add the resources found to the list */
-	for_each_of_pci_range(&parser, &range) {
-
-		if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
-			dev_err(dev, "Maximum memory resources exceeded\n");
-			return -EINVAL;
-		}
-
-		mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
-		if (!mem) {
-			err = -ENOMEM;
-			goto free_resources;
-		}
-
-		of_pci_range_to_resource(&range, node, mem);
-
-		switch (mem->flags & IORESOURCE_TYPE_BITS) {
-		case IORESOURCE_MEM:
-			offset = range.cpu_addr - range.pci_addr;
-			mem_resno++;
-			break;
-		default:
-			err = -EINVAL;
-			break;
-		}
-
-		if (err < 0) {
-			dev_warn(dev, "Invalid resource found %pR\n", mem);
-			continue;
-		}
-
-		err = request_resource(&iomem_resource, mem);
-		if (err)
-			goto free_resources;
-
-		pci_add_resource_offset(&port->resources, mem, offset);
-	}
-
-	/* Get the bus range */
-	if (of_pci_parse_bus_range(node, &port->bus_range)) {
-		u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
-		u8 last;
-
-		last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
-			XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
-
-		port->bus_range = (struct resource) {
-			.name	= node->name,
-			.start	= 0,
-			.end	= last,
-			.flags	= IORESOURCE_BUS,
-		};
-	}
-
-	/* Register bus resource */
-	pci_add_resource(&port->resources, &port->bus_range);
-
-	return 0;
-
-free_resources:
-	release_child_resources(&iomem_resource);
-	resource_list_for_each_entry(win, &port->resources)
-		devm_kfree(dev, win->res);
-	pci_free_resource_list(&port->resources);
-
-	return err;
-}
-
-/**
  * xilinx_pcie_parse_dt - Parse Device tree
  * @port: PCIe port information
  *
@@ -802,6 +707,8 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 	struct hw_pci hw;
 	struct device *dev = &pdev->dev;
 	int err;
+	resource_size_t iobase = 0;
+	LIST_HEAD(res);
 
 	if (!dev->of_node)
 		return -ENODEV;
@@ -826,14 +733,10 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 		return err;
 	}
 
-	/*
-	 * Parse PCI ranges, configuration bus range and
-	 * request their resources
-	 */
-	INIT_LIST_HEAD(&port->resources);
-	err = xilinx_pcie_parse_and_add_res(port);
+	err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff, &res,
+					       &iobase);
 	if (err) {
-		dev_err(dev, "Failed adding resources\n");
+		dev_err(dev, "Getting bridge resources failed\n");
 		return err;
 	}
 
-- 
2.1.1

[PATCH V4 2/5] PCI: xilinx: Removing struct hw_pci structure.

[Bharat Kumar Gogada]

Removing struct hw_pci and adding generic PCI core API's.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
Changes:
Removing architecure dependecy structure struct hw_pci which is ARM 32-bit
specific structure, and adding generic PCI core API's to register to
PCI subsytem.
Removing funtions which are not being used with generic API's.
---
 drivers/pci/host/pcie-xilinx.c | 82 +++++++++---------------------------------
 1 file changed, 16 insertions(+), 66 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 627878d..13fec35 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -111,17 +111,11 @@ struct xilinx_pcie_port {
 	u8 root_busno;
 	struct device *dev;
 	struct irq_domain *irq_domain;
-	struct resource bus_range;
 	struct list_head resources;
 };
 
 static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
 
-static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys)
-{
-	return sys->private_data;
-}
-
 static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
 {
 	return readl(port->reg_base + reg);
@@ -163,7 +157,7 @@ static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
  */
 static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 {
-	struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
+	struct xilinx_pcie_port *port = bus->sysdata;
 
 	/* Check if link is up when trying to access downstream ports */
 	if (bus->number != port->root_busno)
@@ -196,7 +190,7 @@ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
 					 unsigned int devfn, int where)
 {
-	struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
+	struct xilinx_pcie_port *port = bus->sysdata;
 	int relbus;
 
 	if (!xilinx_pcie_valid_device(bus, devfn))
@@ -228,7 +222,7 @@ static void xilinx_pcie_destroy_msi(unsigned int irq)
 
 	if (!test_bit(irq, msi_irq_in_use)) {
 		msi = irq_get_msi_desc(irq);
-		port = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
+		port = msi_desc_to_pci_sysdata(msi);
 		dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
 	} else {
 		clear_bit(irq, msi_irq_in_use);
@@ -277,7 +271,7 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
 				     struct pci_dev *pdev,
 				     struct msi_desc *desc)
 {
-	struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata);
+	struct xilinx_pcie_port *port = pdev->bus->sysdata;
 	unsigned int irq;
 	int hwirq;
 	struct msi_msg msg;
@@ -614,47 +608,6 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
 }
 
 /**
- * xilinx_pcie_setup - Setup memory resources
- * @nr: Bus number
- * @sys: Per controller structure
- *
- * Return: '1' on success and error value on failure
- */
-static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys)
-{
-	struct xilinx_pcie_port *port = sys_to_pcie(sys);
-
-	list_splice_init(&port->resources, &sys->resources);
-
-	return 1;
-}
-
-/**
- * xilinx_pcie_scan_bus - Scan PCIe bus for devices
- * @nr: Bus number
- * @sys: Per controller structure
- *
- * Return: Valid Bus pointer on success and NULL on failure
- */
-static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
-{
-	struct xilinx_pcie_port *port = sys_to_pcie(sys);
-	struct pci_bus *bus;
-
-	port->root_busno = sys->busnr;
-
-	if (IS_ENABLED(CONFIG_PCI_MSI))
-		bus = pci_scan_root_bus_msi(port->dev, sys->busnr,
-					    &xilinx_pcie_ops, sys,
-					    &sys->resources,
-					    &xilinx_pcie_msi_chip);
-	else
-		bus = pci_scan_root_bus(port->dev, sys->busnr,
-					&xilinx_pcie_ops, sys, &sys->resources);
-	return bus;
-}
-
-/**
  * xilinx_pcie_parse_dt - Parse Device tree
  * @port: PCIe port information
  *
@@ -704,8 +657,9 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
 static int xilinx_pcie_probe(struct platform_device *pdev)
 {
 	struct xilinx_pcie_port *port;
-	struct hw_pci hw;
 	struct device *dev = &pdev->dev;
+	struct pci_bus *bus;
+
 	int err;
 	resource_size_t iobase = 0;
 	LIST_HEAD(res);
@@ -739,24 +693,20 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 		dev_err(dev, "Getting bridge resources failed\n");
 		return err;
 	}
-
-	platform_set_drvdata(pdev, port);
-
-	/* Register the device */
-	memset(&hw, 0, sizeof(hw));
-	hw = (struct hw_pci) {
-		.nr_controllers	= 1,
-		.private_data	= (void **)&port,
-		.setup		= xilinx_pcie_setup,
-		.map_irq	= of_irq_parse_and_map_pci,
-		.scan		= xilinx_pcie_scan_bus,
-		.ops		= &xilinx_pcie_ops,
-	};
+	bus = pci_create_root_bus(&pdev->dev, 0,
+				  &xilinx_pcie_ops, port, &res);
+	if (!bus)
+		return -ENOMEM;
 
 #ifdef CONFIG_PCI_MSI
 	xilinx_pcie_msi_chip.dev = port->dev;
+	bus->msi = &xilinx_pcie_msi_chip;
 #endif
-	pci_common_init_dev(dev, &hw);
+	pci_scan_child_bus(bus);
+	pci_assign_unassigned_bus_resources(bus);
+	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+	pci_bus_add_devices(bus);
+	platform_set_drvdata(pdev, port);
 
 	return 0;
 }
-- 
2.1.1

[PATCH V4 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Bharat Kumar Gogada]

Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both
Zynq and Microblaze Architectures.
With these modifications drivers/pci/host/pcie-xilinx.c, will
work on both Zynq and Microblaze Architectures.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>

Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
Changes:
Added #ifdef to pci_fixup_irqs which is ARM specific API.
---
 drivers/pci/host/pcie-xilinx.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 13fec35..8ad50fe 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -704,7 +704,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 #endif
 	pci_scan_child_bus(bus);
 	pci_assign_unassigned_bus_resources(bus);
+#ifndef CONFIG_MICROBLAZE
 	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+#endif
 	pci_bus_add_devices(bus);
 	platform_set_drvdata(pdev, port);
 
-- 
2.1.1

[PATCH V4 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node.

[Bharat Kumar Gogada]

Updated Zynq PCI binding documentation with Microblaze node.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>

Acked-by: Rob Herring <robh@kernel.org>
---
Changes:
Adding Microblaze device tree node Documnetation.
---
 .../devicetree/bindings/pci/xilinx-pcie.txt        | 32 ++++++++++++++++++++--
 1 file changed, 29 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
index 02f979a..ad7c7bf 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -17,7 +17,7 @@ Required properties:
 	Please refer to the standard PCI bus binding document for a more
 	detailed explanation
 
-Optional properties:
+Optional properties for Zynq/Microblaze:
 - bus-range: PCI bus numbers covered
 
 Interrupt controller child node
@@ -38,13 +38,13 @@ the four INTx interrupts in ISR and route them to this domain.
 
 Example:
 ++++++++
-
+Zynq:
 	pci_express: axi-pcie@50000000 {
 		#address-cells = <3>;
 		#size-cells = <2>;
 		#interrupt-cells = <1>;
 		compatible = "xlnx,axi-pcie-host-1.00.a";
-		reg = < 0x50000000 0x10000000 >;
+		reg = < 0x50000000 0x1000000 >;
 		device_type = "pci";
 		interrupts = < 0 52 4 >;
 		interrupt-map-mask = <0 0 0 7>;
@@ -60,3 +60,29 @@ Example:
 			#interrupt-cells = <1>;
 		};
 	};
+
+
+Microblaze:
+	pci_express: axi-pcie@10000000 {
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		compatible = "xlnx,axi-pcie-host-1.00.a";
+		reg = <0x10000000 0x4000000>;
+		device_type = "pci";
+		interrupt-parent = <&microbalze_0_intc>;
+		interrupts = <1 2>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie_intc 1>,
+				<0 0 0 2 &pcie_intc 2>,
+				<0 0 0 3 &pcie_intc 3>,
+				<0 0 0 4 &pcie_intc 4>;
+		ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
+
+		pcie_intc: interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+		};
+
+	};
-- 
2.1.1

[PATCH V4 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bharat Kumar Gogada]

This patch does required modifications to microblaze PCI subsystem, to
work with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze
and Zynq.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Removed pcibios_get_phb_of_node in pci-common.c, using generic version
instead.
Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture.
Modified pcibios_align_resource in pci-common.c, as per generic
architecuture, removed temporary variable.
Removed pci_domain_nr in pci-common.c, instead using generic code.
Added pcibios_add_device in pci-common.c, as per generic architecuture.
Adding Kernel configuration in arch/microblaze as required for generic PCI
domains.
Added kernel configuration for driver to support Microblaze.
---
 arch/microblaze/Kconfig          |  3 +++
 arch/microblaze/pci/pci-common.c | 56 +++++++---------------------------------
 drivers/pci/host/Kconfig         |  2 +-
 3 files changed, 14 insertions(+), 47 deletions(-)

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 0bce820..c3702b9 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -271,6 +271,9 @@ config PCI
 config PCI_DOMAINS
 	def_bool PCI
 
+config PCI_DOMAINS_GENERIC
+	def_bool PCI_DOMAINS
+
 config PCI_SYSCALL
 	def_bool PCI
 
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index ae838ed..35654be 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t address)
 }
 EXPORT_SYMBOL_GPL(pci_address_to_pio);
 
-/*
- * Return the domain number for this bus.
- */
-int pci_domain_nr(struct pci_bus *bus)
-{
-	struct pci_controller *hose = pci_bus_to_host(bus);
-
-	return hose->global_number;
-}
-EXPORT_SYMBOL(pci_domain_nr);
-
 /* This routine is meant to be used early during boot, when the
  * PCI bus numbers have not yet been assigned, and you need to
  * issue PCI config cycles to an OF device.
@@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus *bus)
 
 void pcibios_fixup_bus(struct pci_bus *bus)
 {
-	/* When called from the generic PCI probe, read PCI<->PCI bridge
-	 * bases. This is -not- called when generating the PCI tree from
-	 * the OF device-tree.
-	 */
-	if (bus->self != NULL)
-		pci_read_bridge_bases(bus);
-
-	/* Now fixup the bus bus */
-	pcibios_setup_bus_self(bus);
-
-	/* Now fixup devices on that bus */
-	pcibios_setup_bus_devices(bus);
+	/* nothing to do */
 }
 EXPORT_SYMBOL(pcibios_fixup_bus);
 
-static int skip_isa_ioresource_align(struct pci_dev *dev)
-{
-	return 0;
-}
-
 /*
  * We need to avoid collisions with `mirrored' VGA ports
  * and other strange ISA hardware, so we always want the
@@ -899,20 +872,18 @@ static int skip_isa_ioresource_align(struct pci_dev *dev)
 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 				resource_size_t size, resource_size_t align)
 {
-	struct pci_dev *dev = data;
-	resource_size_t start = res->start;
-
-	if (res->flags & IORESOURCE_IO) {
-		if (skip_isa_ioresource_align(dev))
-			return start;
-		if (start & 0x300)
-			start = (start + 0x3ff) & ~0x3ff;
-	}
-
-	return start;
+	return res->start;
 }
 EXPORT_SYMBOL(pcibios_align_resource);
 
+int pcibios_add_device(struct pci_dev *dev)
+{
+	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+
+	return 0;
+}
+EXPORT_SYMBOL(pcibios_add_device);
+
 /*
  * Reparent resource children of pr that conflict with res
  * under res, and make res replace those children.
@@ -1333,13 +1304,6 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
 		 (unsigned long)hose->io_base_virt - _IO_BASE);
 }
 
-struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
-{
-	struct pci_controller *hose = bus->sysdata;
-
-	return of_node_get(hose->dn);
-}
-
 static void pcibios_scan_phb(struct pci_controller *hose)
 {
 	LIST_HEAD(resources);
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d5e58ba..7c56c2e 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -79,7 +79,7 @@ config PCI_KEYSTONE
 
 config PCIE_XILINX
 	bool "Xilinx AXI PCIe host bridge support"
-	depends on ARCH_ZYNQ
+	depends on ARCH_ZYNQ || MICROBLAZE
 	help
 	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
 	  Host Bridge driver.
-- 
2.1.1

RE: [PATCH V4 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bharat Kumar Gogada]

Ping

> Subject: [PATCH V4 5/5] Microblaze: Modifying microblaze PCI subsytem to
> support generic Xilinx AXI PCIe Host Bridge IP driver
> 
> This patch does required modifications to microblaze PCI subsystem, to work
> with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze and Zynq.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> ---
> Changes:
> Removed pcibios_get_phb_of_node in pci-common.c, using generic version
> instead.
> Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture.
> Modified pcibios_align_resource in pci-common.c, as per generic
> architecuture, removed temporary variable.
> Removed pci_domain_nr in pci-common.c, instead using generic code.
> Added pcibios_add_device in pci-common.c, as per generic architecuture.
> Adding Kernel configuration in arch/microblaze as required for generic PCI
> domains.
> Added kernel configuration for driver to support Microblaze.
> ---
>  arch/microblaze/Kconfig          |  3 +++
>  arch/microblaze/pci/pci-common.c | 56 +++++++---------------------------------
>  drivers/pci/host/Kconfig         |  2 +-
>  3 files changed, 14 insertions(+), 47 deletions(-)
> 
> diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index
> 0bce820..c3702b9 100644
> --- a/arch/microblaze/Kconfig
> +++ b/arch/microblaze/Kconfig
> @@ -271,6 +271,9 @@ config PCI
>  config PCI_DOMAINS
>  	def_bool PCI
> 
> +config PCI_DOMAINS_GENERIC
> +	def_bool PCI_DOMAINS
> +
>  config PCI_SYSCALL
>  	def_bool PCI
> 
> diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-
> common.c
> index ae838ed..35654be 100644
> --- a/arch/microblaze/pci/pci-common.c
> +++ b/arch/microblaze/pci/pci-common.c
> @@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t
> address)  }  EXPORT_SYMBOL_GPL(pci_address_to_pio);
> 
> -/*
> - * Return the domain number for this bus.
> - */
> -int pci_domain_nr(struct pci_bus *bus)
> -{
> -	struct pci_controller *hose = pci_bus_to_host(bus);
> -
> -	return hose->global_number;
> -}
> -EXPORT_SYMBOL(pci_domain_nr);
> -
>  /* This routine is meant to be used early during boot, when the
>   * PCI bus numbers have not yet been assigned, and you need to
>   * issue PCI config cycles to an OF device.
> @@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus
> *bus)
> 
>  void pcibios_fixup_bus(struct pci_bus *bus)  {
> -	/* When called from the generic PCI probe, read PCI<->PCI bridge
> -	 * bases. This is -not- called when generating the PCI tree from
> -	 * the OF device-tree.
> -	 */
> -	if (bus->self != NULL)
> -		pci_read_bridge_bases(bus);
> -
> -	/* Now fixup the bus bus */
> -	pcibios_setup_bus_self(bus);
> -
> -	/* Now fixup devices on that bus */
> -	pcibios_setup_bus_devices(bus);
> +	/* nothing to do */
>  }
>  EXPORT_SYMBOL(pcibios_fixup_bus);
> 
> -static int skip_isa_ioresource_align(struct pci_dev *dev) -{
> -	return 0;
> -}
> -
>  /*
>   * We need to avoid collisions with `mirrored' VGA ports
>   * and other strange ISA hardware, so we always want the @@ -899,20
> +872,18 @@ static int skip_isa_ioresource_align(struct pci_dev *dev)
> resource_size_t pcibios_align_resource(void *data, const struct resource
> *res,
>  				resource_size_t size, resource_size_t align)  {
> -	struct pci_dev *dev = data;
> -	resource_size_t start = res->start;
> -
> -	if (res->flags & IORESOURCE_IO) {
> -		if (skip_isa_ioresource_align(dev))
> -			return start;
> -		if (start & 0x300)
> -			start = (start + 0x3ff) & ~0x3ff;
> -	}
> -
> -	return start;
> +	return res->start;
>  }
>  EXPORT_SYMBOL(pcibios_align_resource);
> 
> +int pcibios_add_device(struct pci_dev *dev) {
> +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(pcibios_add_device);
> +
>  /*
>   * Reparent resource children of pr that conflict with res
>   * under res, and make res replace those children.
> @@ -1333,13 +1304,6 @@ static void pcibios_setup_phb_resources(struct
> pci_controller *hose,
>  		 (unsigned long)hose->io_base_virt - _IO_BASE);  }
> 
> -struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) -{
> -	struct pci_controller *hose = bus->sysdata;
> -
> -	return of_node_get(hose->dn);
> -}
> -
>  static void pcibios_scan_phb(struct pci_controller *hose)  {
>  	LIST_HEAD(resources);
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index
> d5e58ba..7c56c2e 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -79,7 +79,7 @@ config PCI_KEYSTONE
> 
>  config PCIE_XILINX
>  	bool "Xilinx AXI PCIe host bridge support"
> -	depends on ARCH_ZYNQ
> +	depends on ARCH_ZYNQ || MICROBLAZE
>  	help
>  	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
>  	  Host Bridge driver.
> --
> 2.1.1

Re: [PATCH V4 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Mark Rutland]

On Mon, Feb 22, 2016 at 04:01:15PM +0000, Bharat Kumar Gogada wrote:
> Ping

Please trim your To line, and state who you're pinging, and specifically
what you are pinging for. You'll have much better luck with targetted
replies.

Given the number of people in the To line, no-one knows if they're being
poked, or if someone else is. Given the lack of any question/statement
with your ping, it's not clear what you're asking for.

The DT parts of this series already appear to have been reviewed, so
there's no reason to keep myself and other DT maintainers on the To
line for this patch.

Mark.

> 
> > Subject: [PATCH V4 5/5] Microblaze: Modifying microblaze PCI subsytem to
> > support generic Xilinx AXI PCIe Host Bridge IP driver
> > 
> > This patch does required modifications to microblaze PCI subsystem, to work
> > with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze and Zynq.
> > 
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> > ---
> > Changes:
> > Removed pcibios_get_phb_of_node in pci-common.c, using generic version
> > instead.
> > Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture.
> > Modified pcibios_align_resource in pci-common.c, as per generic
> > architecuture, removed temporary variable.
> > Removed pci_domain_nr in pci-common.c, instead using generic code.
> > Added pcibios_add_device in pci-common.c, as per generic architecuture.
> > Adding Kernel configuration in arch/microblaze as required for generic PCI
> > domains.
> > Added kernel configuration for driver to support Microblaze.
> > ---
> >  arch/microblaze/Kconfig          |  3 +++
> >  arch/microblaze/pci/pci-common.c | 56 +++++++---------------------------------
> >  drivers/pci/host/Kconfig         |  2 +-
> >  3 files changed, 14 insertions(+), 47 deletions(-)
> > 
> > diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index
> > 0bce820..c3702b9 100644
> > --- a/arch/microblaze/Kconfig
> > +++ b/arch/microblaze/Kconfig
> > @@ -271,6 +271,9 @@ config PCI
> >  config PCI_DOMAINS
> >  	def_bool PCI
> > 
> > +config PCI_DOMAINS_GENERIC
> > +	def_bool PCI_DOMAINS
> > +
> >  config PCI_SYSCALL
> >  	def_bool PCI
> > 
> > diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-
> > common.c
> > index ae838ed..35654be 100644
> > --- a/arch/microblaze/pci/pci-common.c
> > +++ b/arch/microblaze/pci/pci-common.c
> > @@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t
> > address)  }  EXPORT_SYMBOL_GPL(pci_address_to_pio);
> > 
> > -/*
> > - * Return the domain number for this bus.
> > - */
> > -int pci_domain_nr(struct pci_bus *bus)
> > -{
> > -	struct pci_controller *hose = pci_bus_to_host(bus);
> > -
> > -	return hose->global_number;
> > -}
> > -EXPORT_SYMBOL(pci_domain_nr);
> > -
> >  /* This routine is meant to be used early during boot, when the
> >   * PCI bus numbers have not yet been assigned, and you need to
> >   * issue PCI config cycles to an OF device.
> > @@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus
> > *bus)
> > 
> >  void pcibios_fixup_bus(struct pci_bus *bus)  {
> > -	/* When called from the generic PCI probe, read PCI<->PCI bridge
> > -	 * bases. This is -not- called when generating the PCI tree from
> > -	 * the OF device-tree.
> > -	 */
> > -	if (bus->self != NULL)
> > -		pci_read_bridge_bases(bus);
> > -
> > -	/* Now fixup the bus bus */
> > -	pcibios_setup_bus_self(bus);
> > -
> > -	/* Now fixup devices on that bus */
> > -	pcibios_setup_bus_devices(bus);
> > +	/* nothing to do */
> >  }
> >  EXPORT_SYMBOL(pcibios_fixup_bus);
> > 
> > -static int skip_isa_ioresource_align(struct pci_dev *dev) -{
> > -	return 0;
> > -}
> > -
> >  /*
> >   * We need to avoid collisions with `mirrored' VGA ports
> >   * and other strange ISA hardware, so we always want the @@ -899,20
> > +872,18 @@ static int skip_isa_ioresource_align(struct pci_dev *dev)
> > resource_size_t pcibios_align_resource(void *data, const struct resource
> > *res,
> >  				resource_size_t size, resource_size_t align)  {
> > -	struct pci_dev *dev = data;
> > -	resource_size_t start = res->start;
> > -
> > -	if (res->flags & IORESOURCE_IO) {
> > -		if (skip_isa_ioresource_align(dev))
> > -			return start;
> > -		if (start & 0x300)
> > -			start = (start + 0x3ff) & ~0x3ff;
> > -	}
> > -
> > -	return start;
> > +	return res->start;
> >  }
> >  EXPORT_SYMBOL(pcibios_align_resource);
> > 
> > +int pcibios_add_device(struct pci_dev *dev) {
> > +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL(pcibios_add_device);
> > +
> >  /*
> >   * Reparent resource children of pr that conflict with res
> >   * under res, and make res replace those children.
> > @@ -1333,13 +1304,6 @@ static void pcibios_setup_phb_resources(struct
> > pci_controller *hose,
> >  		 (unsigned long)hose->io_base_virt - _IO_BASE);  }
> > 
> > -struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) -{
> > -	struct pci_controller *hose = bus->sysdata;
> > -
> > -	return of_node_get(hose->dn);
> > -}
> > -
> >  static void pcibios_scan_phb(struct pci_controller *hose)  {
> >  	LIST_HEAD(resources);
> > diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index
> > d5e58ba..7c56c2e 100644
> > --- a/drivers/pci/host/Kconfig
> > +++ b/drivers/pci/host/Kconfig
> > @@ -79,7 +79,7 @@ config PCI_KEYSTONE
> > 
> >  config PCIE_XILINX
> >  	bool "Xilinx AXI PCIe host bridge support"
> > -	depends on ARCH_ZYNQ
> > +	depends on ARCH_ZYNQ || MICROBLAZE
> >  	help
> >  	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
> >  	  Host Bridge driver.
> > --
> > 2.1.1
> 

Re: [PATCH V4 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Michal Simek]

On 11.2.2016 17:28, Bharat Kumar Gogada wrote:
> This patch does required modifications to microblaze PCI subsystem, to
> work with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze
> and Zynq.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> ---
> Changes:
> Removed pcibios_get_phb_of_node in pci-common.c, using generic version
> instead.
> Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture.
> Modified pcibios_align_resource in pci-common.c, as per generic
> architecuture, removed temporary variable.
> Removed pci_domain_nr in pci-common.c, instead using generic code.
> Added pcibios_add_device in pci-common.c, as per generic architecuture.
> Adding Kernel configuration in arch/microblaze as required for generic PCI
> domains.
> Added kernel configuration for driver to support Microblaze.
> ---
>  arch/microblaze/Kconfig          |  3 +++
>  arch/microblaze/pci/pci-common.c | 56 +++++++---------------------------------
>  drivers/pci/host/Kconfig         |  2 +-
>  3 files changed, 14 insertions(+), 47 deletions(-)
> 
> diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
> index 0bce820..c3702b9 100644
> --- a/arch/microblaze/Kconfig
> +++ b/arch/microblaze/Kconfig
> @@ -271,6 +271,9 @@ config PCI
>  config PCI_DOMAINS
>  	def_bool PCI
>  
> +config PCI_DOMAINS_GENERIC
> +	def_bool PCI_DOMAINS
> +
>  config PCI_SYSCALL
>  	def_bool PCI
>  
> diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
> index ae838ed..35654be 100644
> --- a/arch/microblaze/pci/pci-common.c
> +++ b/arch/microblaze/pci/pci-common.c
> @@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t address)
>  }
>  EXPORT_SYMBOL_GPL(pci_address_to_pio);
>  
> -/*
> - * Return the domain number for this bus.
> - */
> -int pci_domain_nr(struct pci_bus *bus)
> -{
> -	struct pci_controller *hose = pci_bus_to_host(bus);
> -
> -	return hose->global_number;
> -}
> -EXPORT_SYMBOL(pci_domain_nr);
> -
>  /* This routine is meant to be used early during boot, when the
>   * PCI bus numbers have not yet been assigned, and you need to
>   * issue PCI config cycles to an OF device.
> @@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus *bus)
>  
>  void pcibios_fixup_bus(struct pci_bus *bus)
>  {
> -	/* When called from the generic PCI probe, read PCI<->PCI bridge
> -	 * bases. This is -not- called when generating the PCI tree from
> -	 * the OF device-tree.
> -	 */
> -	if (bus->self != NULL)
> -		pci_read_bridge_bases(bus);
> -
> -	/* Now fixup the bus bus */
> -	pcibios_setup_bus_self(bus);
> -
> -	/* Now fixup devices on that bus */
> -	pcibios_setup_bus_devices(bus);
> +	/* nothing to do */
>  }
>  EXPORT_SYMBOL(pcibios_fixup_bus);
>  
> -static int skip_isa_ioresource_align(struct pci_dev *dev)
> -{
> -	return 0;
> -}
> -
>  /*
>   * We need to avoid collisions with `mirrored' VGA ports
>   * and other strange ISA hardware, so we always want the
> @@ -899,20 +872,18 @@ static int skip_isa_ioresource_align(struct pci_dev *dev)
>  resource_size_t pcibios_align_resource(void *data, const struct resource *res,
>  				resource_size_t size, resource_size_t align)
>  {
> -	struct pci_dev *dev = data;
> -	resource_size_t start = res->start;
> -
> -	if (res->flags & IORESOURCE_IO) {
> -		if (skip_isa_ioresource_align(dev))
> -			return start;
> -		if (start & 0x300)
> -			start = (start + 0x3ff) & ~0x3ff;
> -	}
> -
> -	return start;
> +	return res->start;
>  }
>  EXPORT_SYMBOL(pcibios_align_resource);
>  
> +int pcibios_add_device(struct pci_dev *dev)
> +{
> +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL(pcibios_add_device);
> +
>  /*
>   * Reparent resource children of pr that conflict with res
>   * under res, and make res replace those children.
> @@ -1333,13 +1304,6 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
>  		 (unsigned long)hose->io_base_virt - _IO_BASE);
>  }
>  
> -struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
> -{
> -	struct pci_controller *hose = bus->sysdata;
> -
> -	return of_node_get(hose->dn);
> -}
> -
>  static void pcibios_scan_phb(struct pci_controller *hose)
>  {
>  	LIST_HEAD(resources);
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index d5e58ba..7c56c2e 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -79,7 +79,7 @@ config PCI_KEYSTONE
>  
>  config PCIE_XILINX
>  	bool "Xilinx AXI PCIe host bridge support"
> -	depends on ARCH_ZYNQ
> +	depends on ARCH_ZYNQ || MICROBLAZE
>  	help
>  	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
>  	  Host Bridge driver.
> 

Less code in arch is better.

Acked-by: Michal Simek <michal.simek@xilinx.com>

Bjorn: Please take this via your tree.

Thanks,
Michal

RE: [PATCH V4 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bharat Kumar Gogada]

Hi Bjorn,

Can you please take this in to your tree.

Thanks,
Bharat

> On 11.2.2016 17:28, Bharat Kumar Gogada wrote:
> > This patch does required modifications to microblaze PCI subsystem, to
> > work with generic driver (drivers/pci/host/pcie-xilinx.c) on
> > Microblaze and Zynq.
> >
> > Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> > Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> > ---
> > Changes:
> > Removed pcibios_get_phb_of_node in pci-common.c, using generic
> version
> > instead.
> > Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture.
> > Modified pcibios_align_resource in pci-common.c, as per generic
> > architecuture, removed temporary variable.
> > Removed pci_domain_nr in pci-common.c, instead using generic code.
> > Added pcibios_add_device in pci-common.c, as per generic architecuture.
> > Adding Kernel configuration in arch/microblaze as required for generic
> > PCI domains.
> > Added kernel configuration for driver to support Microblaze.
> > ---
> >  arch/microblaze/Kconfig          |  3 +++
> >  arch/microblaze/pci/pci-common.c | 56 +++++++-------------------------------
> --
> >  drivers/pci/host/Kconfig         |  2 +-
> >  3 files changed, 14 insertions(+), 47 deletions(-)
> >
> > diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index
> > 0bce820..c3702b9 100644
> > --- a/arch/microblaze/Kconfig
> > +++ b/arch/microblaze/Kconfig
> > @@ -271,6 +271,9 @@ config PCI
> >  config PCI_DOMAINS
> >  	def_bool PCI
> >
> > +config PCI_DOMAINS_GENERIC
> > +	def_bool PCI_DOMAINS
> > +
> >  config PCI_SYSCALL
> >  	def_bool PCI
> >
> > diff --git a/arch/microblaze/pci/pci-common.c
> > b/arch/microblaze/pci/pci-common.c
> > index ae838ed..35654be 100644
> > --- a/arch/microblaze/pci/pci-common.c
> > +++ b/arch/microblaze/pci/pci-common.c
> > @@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t
> > address)  }  EXPORT_SYMBOL_GPL(pci_address_to_pio);
> >
> > -/*
> > - * Return the domain number for this bus.
> > - */
> > -int pci_domain_nr(struct pci_bus *bus) -{
> > -	struct pci_controller *hose = pci_bus_to_host(bus);
> > -
> > -	return hose->global_number;
> > -}
> > -EXPORT_SYMBOL(pci_domain_nr);
> > -
> >  /* This routine is meant to be used early during boot, when the
> >   * PCI bus numbers have not yet been assigned, and you need to
> >   * issue PCI config cycles to an OF device.
> > @@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus
> > *bus)
> >
> >  void pcibios_fixup_bus(struct pci_bus *bus)  {
> > -	/* When called from the generic PCI probe, read PCI<->PCI bridge
> > -	 * bases. This is -not- called when generating the PCI tree from
> > -	 * the OF device-tree.
> > -	 */
> > -	if (bus->self != NULL)
> > -		pci_read_bridge_bases(bus);
> > -
> > -	/* Now fixup the bus bus */
> > -	pcibios_setup_bus_self(bus);
> > -
> > -	/* Now fixup devices on that bus */
> > -	pcibios_setup_bus_devices(bus);
> > +	/* nothing to do */
> >  }
> >  EXPORT_SYMBOL(pcibios_fixup_bus);
> >
> > -static int skip_isa_ioresource_align(struct pci_dev *dev) -{
> > -	return 0;
> > -}
> > -
> >  /*
> >   * We need to avoid collisions with `mirrored' VGA ports
> >   * and other strange ISA hardware, so we always want the @@ -899,20
> > +872,18 @@ static int skip_isa_ioresource_align(struct pci_dev *dev)
> > resource_size_t pcibios_align_resource(void *data, const struct resource
> *res,
> >  				resource_size_t size, resource_size_t align)  {
> > -	struct pci_dev *dev = data;
> > -	resource_size_t start = res->start;
> > -
> > -	if (res->flags & IORESOURCE_IO) {
> > -		if (skip_isa_ioresource_align(dev))
> > -			return start;
> > -		if (start & 0x300)
> > -			start = (start + 0x3ff) & ~0x3ff;
> > -	}
> > -
> > -	return start;
> > +	return res->start;
> >  }
> >  EXPORT_SYMBOL(pcibios_align_resource);
> >
> > +int pcibios_add_device(struct pci_dev *dev) {
> > +	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
> > +
> > +	return 0;
> > +}
> > +EXPORT_SYMBOL(pcibios_add_device);
> > +
> >  /*
> >   * Reparent resource children of pr that conflict with res
> >   * under res, and make res replace those children.
> > @@ -1333,13 +1304,6 @@ static void pcibios_setup_phb_resources(struct
> pci_controller *hose,
> >  		 (unsigned long)hose->io_base_virt - _IO_BASE);  }
> >
> > -struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus) -{
> > -	struct pci_controller *hose = bus->sysdata;
> > -
> > -	return of_node_get(hose->dn);
> > -}
> > -
> >  static void pcibios_scan_phb(struct pci_controller *hose)  {
> >  	LIST_HEAD(resources);
> > diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index
> > d5e58ba..7c56c2e 100644
> > --- a/drivers/pci/host/Kconfig
> > +++ b/drivers/pci/host/Kconfig
> > @@ -79,7 +79,7 @@ config PCI_KEYSTONE
> >
> >  config PCIE_XILINX
> >  	bool "Xilinx AXI PCIe host bridge support"
> > -	depends on ARCH_ZYNQ
> > +	depends on ARCH_ZYNQ || MICROBLAZE
> >  	help
> >  	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
> >  	  Host Bridge driver.
> >
> 
> Less code in arch is better.
> 
> Acked-by: Michal Simek <michal.simek@xilinx.com>
> 
> Bjorn: Please take this via your tree.
> 
> Thanks,
> Michal

Re: [PATCH V4 0/5] PCIe Xilinx generic driver for Microblaze and

[Bjorn Helgaas]

On Thu, Feb 11, 2016 at 09:58:06PM +0530, Bharat Kumar Gogada wrote:
> This patch series does modifications to pcie-xilinx.c, to support common
> driver on both Zynq and Microblaze architectures.
> Microblaze pci-common.c has been modified to support generic driver.
> 
> Bharat Kumar Gogada (5):
>   PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function
>   PCI: xilinx: Removing struct hw_pci structure.
>   PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both
>      Zynq and Microblaze
>   PCI: xilinx: Updating Zynq PCI binding documentation with 
>     Microblaze node.
>   Microblaze: Modifying microblaze PCI subsytem to support  generic
>     Xilinx  AXI PCIe Host Bridge IP driver
> 
>  .../devicetree/bindings/pci/xilinx-pcie.txt        |  32 +++-
>  arch/microblaze/Kconfig                            |   3 +
>  arch/microblaze/pci/pci-common.c                   |  56 ++----
>  drivers/pci/host/Kconfig                           |   2 +-
>  drivers/pci/host/pcie-xilinx.c                     | 191 +++------------------
>  5 files changed, 66 insertions(+), 218 deletions(-)

I applied this series to my pci/host-xilinx branch for v4.6.

Michal, you only explicitly acked the last patch, but that only makes
sense if I apply the whole series, so I applied your ack to all the
patches.

Someday somebody should rework pci_fixup_irqs() so that doesn't have
to be arch-dependent.

I reworked the changelogs as below.

Bjorn


commit 01cf9d524ff0
Author: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Date:   Thu Feb 11 21:58:11 2016 +0530

    microblaze/PCI: Support generic Xilinx AXI PCIe Host Bridge IP driver
    
    Modify the Microblaze PCI subsystem to work with the generic
    drivers/pci/host/pcie-xilinx.c driver on Microblaze and Zynq.
    
    [bhelgaas: changelog]
    Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
    Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    Acked-by: Michal Simek <michal.simek@xilinx.com>

commit e5d4b2006c97
Author: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Date:   Thu Feb 11 21:58:10 2016 +0530

    PCI: xilinx: Update Zynq binding with Microblaze node
    
    Update Zynq PCI binding documentation with Microblaze node.
    
    [bhelgaas: fix "microbalze_0_intc" typo]
    Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
    Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    Acked-by: Rob Herring <robh@kernel.org>
    Acked-by: Michal Simek <michal.simek@xilinx.com>

commit 2c51391d2559
Author: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Date:   Thu Feb 11 21:58:09 2016 +0530

    PCI: xilinx: Don't call pci_fixup_irqs() on Microblaze
    
    The Xilinx AXI PCIe Host Bridge Soft IP driver was previously only
    supported on ARM (in particular, on ARCH_ZYNC), and pci_fixup_irqs() is
    available there.  But Microblaze will do IRQ fixup in pcibios_add_device(),
    so pci_fixup_irqs() is not available on Microblaze.
    
    Don't call pci_fixup_irqs() on Microblaze, so the driver can work on both
    Zynq and Microblaze Architectures.
    
    [bhelgaas: revise changelog to show similarity to bdb8a1844f31 ("PCI: iproc: Call pci_fixup_irqs() for ARM64 as well as ARM")]
    Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
    Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    Reviewed-by: Arnd Bergmann <arnd@arndb.de>
    Acked-by: Michal Simek <michal.simek@xilinx.com>

commit 4c01f3b089a0
Author: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Date:   Thu Feb 11 21:58:08 2016 +0530

    PCI: xilinx: Remove dependency on ARM-specific struct hw_pci
    
    The Xilinx PCIe host controller driver uses pci_common_init_dev(), which
    is ARM-specific and requires the ARM struct hw_pci.  The part of
    pci_common_init_dev() that is needed is limited and can be done here
    without using hw_pci.
    
    Create and scan the root bus directly without using the ARM
    pci_common_init_dev() interface.
    
    [bhelgaas: revise changelog to show similarity to 79953dd22c1d ("PCI: rcar: Remove dependency on ARM-specific struct hw_pci")]
    Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
    Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    Reviewed-by: Arnd Bergmann <arnd@arndb.de>
    Acked-by: Michal Simek <michal.simek@xilinx.com>

commit 0259882e342e
Author: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
Date:   Thu Feb 11 21:58:07 2016 +0530

    PCI: xilinx: Use of_pci_get_host_bridge_resources() to parse DT
    
    Use the new of_pci_get_host_bridge_resources() API in place of the PCI OF
    DT parser.
    
    [bhelgaas: revise changelog to show similarity to 0021d22b73d6 ("PCI: designware: Use of_pci_get_host_bridge_resources() to parse DT")]
    Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
    Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    Reviewed-by: Arnd Bergmann <arnd@arndb.de>
    Acked-by: Michal Simek <michal.simek@xilinx.com>

RE: [PATCH V4 0/5] PCIe Xilinx generic driver for Microblaze and

[Bharat Kumar Gogada]

Thanks Bjorn.
Thanks to Bjorn Helgaas and Arnd Bergmann for your review and suggestions.

Bharat

> On Thu, Feb 11, 2016 at 09:58:06PM +0530, Bharat Kumar Gogada wrote:
> > This patch series does modifications to pcie-xilinx.c, to support common
> > driver on both Zynq and Microblaze architectures.
> > Microblaze pci-common.c has been modified to support generic driver.
> >
> > Bharat Kumar Gogada (5):
> >   PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function
> >   PCI: xilinx: Removing struct hw_pci structure.
> >   PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both
> >      Zynq and Microblaze
> >   PCI: xilinx: Updating Zynq PCI binding documentation with
> >     Microblaze node.
> >   Microblaze: Modifying microblaze PCI subsytem to support  generic
> >     Xilinx  AXI PCIe Host Bridge IP driver
> >
> >  .../devicetree/bindings/pci/xilinx-pcie.txt        |  32 +++-
> >  arch/microblaze/Kconfig                            |   3 +
> >  arch/microblaze/pci/pci-common.c                   |  56 ++----
> >  drivers/pci/host/Kconfig                           |   2 +-
> >  drivers/pci/host/pcie-xilinx.c                     | 191 +++------------------
> >  5 files changed, 66 insertions(+), 218 deletions(-)
> 
> I applied this series to my pci/host-xilinx branch for v4.6.
> 
> Michal, you only explicitly acked the last patch, but that only makes
> sense if I apply the whole series, so I applied your ack to all the
> patches.
> 
> Someday somebody should rework pci_fixup_irqs() so that doesn't have
> to be arch-dependent.
> 
> I reworked the changelogs as below.
> 
> Bjorn
> 
> 
> commit 01cf9d524ff0
> Author: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> Date:   Thu Feb 11 21:58:11 2016 +0530
> 
>     microblaze/PCI: Support generic Xilinx AXI PCIe Host Bridge IP driver
> 
>     Modify the Microblaze PCI subsystem to work with the generic
>     drivers/pci/host/pcie-xilinx.c driver on Microblaze and Zynq.
> 
>     [bhelgaas: changelog]
>     Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
>     Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
>     Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>     Acked-by: Michal Simek <michal.simek@xilinx.com>
> 
> commit e5d4b2006c97
> Author: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> Date:   Thu Feb 11 21:58:10 2016 +0530
> 
>     PCI: xilinx: Update Zynq binding with Microblaze node
> 
>     Update Zynq PCI binding documentation with Microblaze node.
> 
>     [bhelgaas: fix "microbalze_0_intc" typo]
>     Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
>     Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
>     Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>     Acked-by: Rob Herring <robh@kernel.org>
>     Acked-by: Michal Simek <michal.simek@xilinx.com>
> 
> commit 2c51391d2559
> Author: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> Date:   Thu Feb 11 21:58:09 2016 +0530
> 
>     PCI: xilinx: Don't call pci_fixup_irqs() on Microblaze
> 
>     The Xilinx AXI PCIe Host Bridge Soft IP driver was previously only
>     supported on ARM (in particular, on ARCH_ZYNC), and pci_fixup_irqs() is
>     available there.  But Microblaze will do IRQ fixup in pcibios_add_device(),
>     so pci_fixup_irqs() is not available on Microblaze.
> 
>     Don't call pci_fixup_irqs() on Microblaze, so the driver can work on both
>     Zynq and Microblaze Architectures.
> 
>     [bhelgaas: revise changelog to show similarity to bdb8a1844f31 ("PCI: iproc:
> Call pci_fixup_irqs() for ARM64 as well as ARM")]
>     Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
>     Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
>     Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>     Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>     Acked-by: Michal Simek <michal.simek@xilinx.com>
> 
> commit 4c01f3b089a0
> Author: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> Date:   Thu Feb 11 21:58:08 2016 +0530
> 
>     PCI: xilinx: Remove dependency on ARM-specific struct hw_pci
> 
>     The Xilinx PCIe host controller driver uses pci_common_init_dev(), which
>     is ARM-specific and requires the ARM struct hw_pci.  The part of
>     pci_common_init_dev() that is needed is limited and can be done here
>     without using hw_pci.
> 
>     Create and scan the root bus directly without using the ARM
>     pci_common_init_dev() interface.
> 
>     [bhelgaas: revise changelog to show similarity to 79953dd22c1d ("PCI: rcar:
> Remove dependency on ARM-specific struct hw_pci")]
>     Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
>     Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
>     Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>     Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>     Acked-by: Michal Simek <michal.simek@xilinx.com>
> 
> commit 0259882e342e
> Author: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
> Date:   Thu Feb 11 21:58:07 2016 +0530
> 
>     PCI: xilinx: Use of_pci_get_host_bridge_resources() to parse DT
> 
>     Use the new of_pci_get_host_bridge_resources() API in place of the PCI
> OF
>     DT parser.
> 
>     [bhelgaas: revise changelog to show similarity to 0021d22b73d6 ("PCI:
> designware: Use of_pci_get_host_bridge_resources() to parse DT")]
>     Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
>     Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
>     Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>     Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>     Acked-by: Michal Simek <michal.simek@xilinx.com>

Re: [PATCH V4 0/5] PCIe Xilinx generic driver for Microblaze and

[Michal Simek]

On 8.3.2016 21:34, Bjorn Helgaas wrote:
> On Thu, Feb 11, 2016 at 09:58:06PM +0530, Bharat Kumar Gogada wrote:
>> This patch series does modifications to pcie-xilinx.c, to support common
>> driver on both Zynq and Microblaze architectures.
>> Microblaze pci-common.c has been modified to support generic driver.
>>
>> Bharat Kumar Gogada (5):
>>   PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function
>>   PCI: xilinx: Removing struct hw_pci structure.
>>   PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both
>>      Zynq and Microblaze
>>   PCI: xilinx: Updating Zynq PCI binding documentation with 
>>     Microblaze node.
>>   Microblaze: Modifying microblaze PCI subsytem to support  generic
>>     Xilinx  AXI PCIe Host Bridge IP driver
>>
>>  .../devicetree/bindings/pci/xilinx-pcie.txt        |  32 +++-
>>  arch/microblaze/Kconfig                            |   3 +
>>  arch/microblaze/pci/pci-common.c                   |  56 ++----
>>  drivers/pci/host/Kconfig                           |   2 +-
>>  drivers/pci/host/pcie-xilinx.c                     | 191 +++------------------
>>  5 files changed, 66 insertions(+), 218 deletions(-)
> 
> I applied this series to my pci/host-xilinx branch for v4.6.
> 
> Michal, you only explicitly acked the last patch, but that only makes
> sense if I apply the whole series, so I applied your ack to all the
> patches.

No problem.

Thanks,
Michal