From: Sinan Kaya <okaya@codeaurora.org>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: linux-acpi@vger.kernel.org, timur@codeaurora.org,
cov@codeaurora.org, linux-pci@vger.kernel.org,
ravikanth.nalla@hpe.com, lenb@kernel.org, harish.k@hpe.com,
ashwin.reghunandanan@hpe.com, bhelgaas@google.com,
rjw@rjwysocki.net, linux-kernel@vger.kernel.org,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH V2] acpi, pci, irq: account for early penalty assignment
Date: Tue, 8 Mar 2016 14:04:56 -0500 [thread overview]
Message-ID: <56DF2258.8020004@codeaurora.org> (raw)
In-Reply-To: <20160308002909.GA13250@localhost>
>>>> I think there are two issues here that should be teased apart a bit
>>>> more:
>>>>
>>>> 1) Trigger settings: If the IRQ is configured as anything other than
>>>> level-triggered, active-low, we can't use it at all for a PCI
>>>> interrupt, and we should return an "infinite" penalty. We currently
>>>> increase the penalty for the SCI IRQ if it's not level/low, but
>>>> doesn't it apply to *all* IRQs, not just the SCI IRQ?
>>>
>>> It makes sense for SCI as it is Intel specific.
>>>
>>> Unfortunately, this cannot be done in an arch independent way. Of course,
>>> ARM had to implement its own thing. While level-triggered, active-low is
>>> good for intel world, it is not for the ARM world. ARM uses active-high
>>> level triggered.
>>
>> I'm confused. I don't think SCI is Intel-specific. Per PCI Spec
>> r3.0, sec 2.2.6, PCI interrupts are level-sensitive, asserted low.
>> Per ACPI Spec v3.0, sec 2.1, the SCI is an "active, low, shareable,
>> level interrupt".
>>
>> Are you saying SCI is active-high on ARM? If so, I don't think that's
>> necessarily a huge problem, although we'd have to audit the ACPI code
>> to make sure we handle it correctly.
We don't have an SCI interrupt on ARM. That's why, I assumed it is an Intel specific
interrupt. However, all legacy interrupts are active-high level sensitive. This is a
limitation of the ARM GIC Interrupt Controller.
Here is what a PCI Link object looks like.
Device(LN0D){
Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
Name(_UID, 4)
Name(_PRS, ResourceTemplate(){
Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) {123}
})
Method(_DIS) {}
Method(_CRS) { Return (_PRS) }
Method(_SRS, 1) {}
}
>>
>> The point here is that a PCI Interrupt Link can only use an IRQ that
>> is level-triggered, active low. If an IRQ is already set to any other
>> state, whether for an ISA device or for an active-high SCI, we can't
>> use it for a PCI Interrupt Link.
Unfortunately, this still doesn't hold.
A patch is long overdue for this series. I'll post v3. We can go from there.
--
Sinan Kaya
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2016-03-08 19:04 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-18 13:19 [PATCH V2] acpi, pci, irq: account for early penalty assignment Sinan Kaya
2016-02-18 15:12 ` Timur Tabi
2016-02-18 16:39 ` Rafael J. Wysocki
2016-02-18 16:43 ` Sinan Kaya
2016-02-29 19:24 ` Bjorn Helgaas
2016-02-29 20:08 ` Sinan Kaya
2016-02-29 22:34 ` Bjorn Helgaas
2016-03-01 18:49 ` Sinan Kaya
2016-03-01 19:43 ` Bjorn Helgaas
2016-03-02 18:31 ` Sinan Kaya
2016-03-03 3:14 ` Sinan Kaya
2016-03-03 14:48 ` Sinan Kaya
2016-03-03 15:10 ` Bjorn Helgaas
2016-03-03 15:12 ` Sinan Kaya
2016-03-03 17:29 ` Sinan Kaya
2016-03-04 18:09 ` Bjorn Helgaas
2016-03-07 16:55 ` Sinan Kaya
2016-03-08 0:25 ` Bjorn Helgaas
2016-03-08 0:29 ` Bjorn Helgaas
2016-03-08 19:04 ` Sinan Kaya [this message]
2016-03-08 20:59 ` Rafael J. Wysocki
2016-03-09 0:45 ` Sinan Kaya
2016-03-08 8:22 ` Thomas Gleixner
2016-03-08 17:35 ` Bjorn Helgaas
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