Question about cacheline size in PCIe SAS card

[wangyijing <wangyijing@huawei.com>]

Hi all, we found a question about PCIe cacheline, the cacheline here is mean the
configure space register at offset 0x0C in type 0 and type 1 configure space header.

We did a hotplug in our platform for PCIe SAS controller, this sas controller has
SSD disks and the disk sector is 520 bytes. Defaultly, BIOS set cacheline size to
64bytes, we test the IO read(io size is 128k/256k), the bandwith is 6G.
After hotplug, the cacheline size in SAS controller changes to 0(default after #RST),
and we test the IO read again, the bandwith changes to 5.2G.

We Tested other SAS controller which is not 520 bytes sector, we didn't found this issue,
and I grep the PCI_CACHE_LINE_SIZE in kernel, I found most of code change the PCI_CACHE_LINE_SIZE
are device driver, like net, ata, and some arm pci controller.

In PCI 3.0 spec, I found there are descriptions about cacheline size releated to performance,
but in PCIe 3.0 spec, there is nothing related to cacheline size.

I wonder what's cacheline register roles in PCIe spec, how can we use it correctly ?

Thanks!
Yijing.