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b=IoPqVN3OFLenlQ2UfnYSu7kGwcjXbdh22zg81jEPmpiMTZx7oDmEXiqrizH7AzxSeO+ueQFjueqm3Z75RDuChUg0zZxHm2VhZQLQWqIU7gJTts0La59MPLggORPC0xNcxvf+WMU/JE99+Ot5SBjieNFXwnpo2DMx211p5CjK5kZ/nWsnjAM32ng9a2Css04uXlt23CU6NKEoJV1zerjGo2Dsze29LNumsUP3fy/cNhJUB1P7/L3mRDMG8rxbZAev+DIZhvfJFcVYqpGkbYGYLT4+YVMtq8d3njihGaK+w5rLvZx0mlLr+U/m4FQuBte6dRxltIgsvRKqnvAk4heMHg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from DS2PR12MB9750.namprd12.prod.outlook.com (2603:10b6:8:2b0::12) by SJ1PR12MB6100.namprd12.prod.outlook.com (2603:10b6:a03:45d::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9870.27; Tue, 5 May 2026 08:50:58 +0000 Received: from DS2PR12MB9750.namprd12.prod.outlook.com ([fe80::56a8:d6bf:e24c:b391]) by DS2PR12MB9750.namprd12.prod.outlook.com ([fe80::56a8:d6bf:e24c:b391%6]) with mapi id 15.20.9870.023; Tue, 5 May 2026 08:50:58 +0000 Message-ID: <58f54b48-7c06-4564-9ec9-d1efb1cb8687@nvidia.com> Date: Tue, 5 May 2026 09:50:52 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency To: Manikanta Maddireddy , bhelgaas@google.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, thierry.reding@gmail.com, kishon@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, Frank.Li@nxp.com, den@valinux.co.jp, hongxing.zhu@nxp.com, jingoohan1@gmail.com, vidyas@nvidia.com, cassel@kernel.org, 18255117159@163.com Cc: linux-pci@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260410073330.837238-1-mmaddireddy@nvidia.com> From: Jon Hunter Content-Language: en-US In-Reply-To: <20260410073330.837238-1-mmaddireddy@nvidia.com> Content-Type: text/plain; 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Convert the value from nanoseconds Is the 'instead of of_data' relevant here? > to the hardware encoding (log2(us) + 1, 3-bit field). If the property is Its says 'nanoseconds', but the equation above references uS. I see below you convert ns to uS and then take the log2. So I guess this should be 'log2(ns/1000) + 1'. Also the '3-bit field' bit is not very clear. So may be ... "Convert the value from nanoseconds to a hardware encoded 3-bit value that is equal to log2(ns/1000) + 1. If the property is absent or greater than 7 (the maximum latency value supported), then default to 7." > absent, default to 7 (maximum latency). > > Signed-off-by: Manikanta Maddireddy > Signed-off-by: Manivannan Sadhasivam > Link: https://patch.msgid.link/20260324191000.1095768-10-mmaddireddy@nvidia.com > --- > drivers/pci/controller/dwc/pcie-tegra194.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index 50c5ef12552b..f171f7e32b75 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -18,6 +18,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -272,6 +273,7 @@ struct tegra_pcie_dw { > u32 aspm_cmrt; > u32 aspm_pwr_on_t; > u32 aspm_l0s_enter_lat; > + u32 aspm_l1_enter_lat; > > struct regulator *pex_ctl_supply; > struct regulator *slot_ctl_3v3; > @@ -710,6 +712,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) > val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR); > val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK; > val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); > + val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK; > + val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT); > val |= PORT_AFR_ENTER_ASPM; > dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val); > } > @@ -1110,6 +1114,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) > { > struct platform_device *pdev = to_platform_device(pcie->dev); > struct device_node *np = pcie->dev->of_node; > + u32 val; > int ret; > > pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); > @@ -1136,6 +1141,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie) > dev_info(pcie->dev, > "Failed to read ASPM L0s Entrance latency: %d\n", ret); > > + /* Default to max latency of 7. */ > + pcie->aspm_l1_enter_lat = 7; > + ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val); > + if (!ret) { > + u32 us = max(val / 1000, 1U); > + > + pcie->aspm_l1_enter_lat = min(ilog2(us) + 1, 7); > + } > + > ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); > if (ret < 0) { > dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); -- nvpublic