From: Mohit Kumar <mohit.kumar@st.com>
To: <bhelgaas@google.com>
Cc: Mohit Kumar <mohit.kumar@st.com>, <spear-devel@list.st.com>,
<linux-pci@vger.kernel.org>
Subject: [PATCH V2 1/2] PCI: designware: Fix comment for setting number of lanes
Date: Thu, 27 Feb 2014 11:31:27 +0530 [thread overview]
Message-ID: <60f5de0e4513e1a55c51c3c80c3a51cf595dbe59.1392904207.git.mohit.kumar@st.com> (raw)
In-Reply-To: <cover.1392904207.git.mohit.kumar@st.com>
Corrects comment for setting number of lanes.
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: spear-devel@list.st.com
Cc: linux-pci@vger.kernel.org
---
drivers/pci/host/pcie-designware.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 6d23d8c..391966f 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -766,7 +766,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 membase;
u32 memlimit;
- /* set the number of lines as 4 */
+ /* set the number of lanes */
dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
val &= ~PORT_LINK_MODE_MASK;
switch (pp->lanes) {
--
1.7.3.4
next prev parent reply other threads:[~2014-02-27 6:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-27 6:01 [PATCH V2 0/2] PCI: dessignware: fixes and cleanup Mohit Kumar
2014-02-27 6:01 ` Mohit Kumar [this message]
2014-02-27 6:01 ` [PATCH V2 2/2] PCI: designware: Fix iATU programming for cfg1, io and mem viewport Mohit Kumar
2014-03-24 4:02 ` [PATCH V2 0/2] PCI: dessignware: fixes and cleanup Mohit KUMAR DCG
2014-04-04 16:06 ` Bjorn Helgaas
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