* [PATCH v2 0/5] Add MSI-X support for cadence EP driver
@ 2018-08-15 13:46 Alan Douglas
2018-08-15 16:55 ` Ramon Fried
0 siblings, 1 reply; 6+ messages in thread
From: Alan Douglas @ 2018-08-15 13:46 UTC (permalink / raw)
To: bhelgaas
Cc: kishon, lorenzo.pieralisi, linux-pci, gustavo.pimentel,
cyrille.pitchen, stelford, Alan Douglas
The patch implements MSI-X support in the cadence endpoint driver.
This patch depends on on Gustavo Pimentel's patch series adding MSI-X
support for EP ("Add MSI-X support on pcitest tool")
It also adds fixes for MSI issues discovered during testing of MSI-X
- Use AXI region 0 for interrupt signalling
- Write MSI and MSI-X with 32bit value rather than 16bit
- Check for masking before sending MSI or MSI-X
- Check link is up before sending IRQ
Changes since v1:
- Rebased on 4.18-rc1
- Update commit log to mark first 4 patches as fixes
- Correct formatting issues pointed out by checkpatch --strict
Alan Douglas (5):
PCI: cadence: Use AXI region 0 to signal interrupts from EP
PCI: cadence: Write MSI data with 32bits
PCI: cadence: Check whether MSI is masked before sending it
PCI: cadence: Check link is up before sending IRQ from EP
PCI: cadence: Add MSI-X capability to EP driver
drivers/pci/controller/pcie-cadence-ep.c | 131 +++++++++++++++++++++++++++++--
drivers/pci/controller/pcie-cadence.h | 1 +
2 files changed, 125 insertions(+), 7 deletions(-)
--
1.9.0
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v2 0/5] Add MSI-X support for cadence EP driver 2018-08-15 13:46 [PATCH v2 0/5] Add MSI-X support for cadence EP driver Alan Douglas @ 2018-08-15 16:55 ` Ramon Fried 2018-08-16 14:28 ` Alan Douglas 0 siblings, 1 reply; 6+ messages in thread From: Ramon Fried @ 2018-08-15 16:55 UTC (permalink / raw) To: Alan Douglas, bhelgaas Cc: kishon, lorenzo.pieralisi, linux-pci, gustavo.pimentel, cyrille.pitchen, stelford On August 15, 2018 4:46:21 PM GMT+03:00, Alan Douglas <adouglas@cadence=2Ec= om> wrote: >The patch implements MSI-X support in the cadence endpoint driver=2E > >This patch depends on on Gustavo Pimentel's patch series adding MSI-X >support for EP ("Add MSI-X support on pcitest tool")=20 > >It also adds fixes for MSI issues discovered during testing of MSI-X > - Use AXI region 0 for interrupt signalling > - Write MSI and MSI-X with 32bit value rather than 16bit > - Check for masking before sending MSI or MSI-X > - Check link is up before sending IRQ > Hi=2E=20 AFAIK the BIOS allocates physical memory for the bars=2E Assuming that the= MSIx bar is only mapped after kernel boots on the endpoint, could it be to= o late?=20 Do we need to trigger re-enumeration of the PCI bus from host side when wo= rking with this as an endpoint?=20 Thanks,=20 Ramon=20 >Changes since v1: > - Rebased on 4=2E18-rc1 > - Update commit log to mark first 4 patches as fixes > - Correct formatting issues pointed out by checkpatch --strict > >Alan Douglas (5): > PCI: cadence: Use AXI region 0 to signal interrupts from EP > PCI: cadence: Write MSI data with 32bits > PCI: cadence: Check whether MSI is masked before sending it > PCI: cadence: Check link is up before sending IRQ from EP > PCI: cadence: Add MSI-X capability to EP driver > >drivers/pci/controller/pcie-cadence-ep=2Ec | 131 >+++++++++++++++++++++++++++++-- > drivers/pci/controller/pcie-cadence=2Eh | 1 + > 2 files changed, 125 insertions(+), 7 deletions(-) --=20 Sent from my Android device with K-9 Mail=2E Please excuse my brevity=2E ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v2 0/5] Add MSI-X support for cadence EP driver 2018-08-15 16:55 ` Ramon Fried @ 2018-08-16 14:28 ` Alan Douglas [not found] ` <CA+Kvs9m=jECCcy6RCrtKvJOAwt5Fr8XFFkkijMy3MFe9trav5g@mail.gmail.com> 0 siblings, 1 reply; 6+ messages in thread From: Alan Douglas @ 2018-08-16 14:28 UTC (permalink / raw) To: Ramon Fried, bhelgaas@google.com Cc: kishon@ti.com, lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org, gustavo.pimentel@synopsys.com, cyrille.pitchen@bootlin.com, Scott Telford SGkgUmFtb24sDQoNCk9uIDE1IEF1Z3VzdCAyMDE4IDE3OjU2LCBSYW1vbiBGcmllZCB3cm90ZToN Cj4gT24gQXVndXN0IDE1LCAyMDE4IDQ6NDY6MjEgUE0gR01UKzAzOjAwLCBBbGFuIERvdWdsYXMg PGFkb3VnbGFzQGNhZGVuY2UuY29tPiB3cm90ZToNCj4gPlRoZSBwYXRjaCBpbXBsZW1lbnRzIE1T SS1YIHN1cHBvcnQgaW4gdGhlIGNhZGVuY2UgZW5kcG9pbnQgZHJpdmVyLg0KPiA+DQo+ID5UaGlz IHBhdGNoIGRlcGVuZHMgb24gb24gR3VzdGF2byBQaW1lbnRlbCdzIHBhdGNoIHNlcmllcyBhZGRp bmcgTVNJLVgNCj4gPnN1cHBvcnQgZm9yIEVQICgiQWRkIE1TSS1YIHN1cHBvcnQgb24gcGNpdGVz dCB0b29sIikNCj4gPg0KPiA+SXQgYWxzbyBhZGRzIGZpeGVzIGZvciBNU0kgaXNzdWVzIGRpc2Nv dmVyZWQgZHVyaW5nIHRlc3Rpbmcgb2YgTVNJLVgNCj4gPiAgLSBVc2UgQVhJIHJlZ2lvbiAwIGZv ciBpbnRlcnJ1cHQgc2lnbmFsbGluZw0KPiA+ICAtIFdyaXRlIE1TSSBhbmQgTVNJLVggd2l0aCAz MmJpdCB2YWx1ZSByYXRoZXIgdGhhbiAxNmJpdA0KPiA+ICAtIENoZWNrIGZvciBtYXNraW5nIGJl Zm9yZSBzZW5kaW5nIE1TSSBvciBNU0ktWA0KPiA+ICAtIENoZWNrIGxpbmsgaXMgdXAgYmVmb3Jl IHNlbmRpbmcgSVJRDQo+ID4NCj4gSGkuDQo+IEFGQUlLIHRoZSBCSU9TIGFsbG9jYXRlcyBwaHlz aWNhbCBtZW1vcnkgZm9yIHRoZSBiYXJzLiBBc3N1bWluZyB0aGF0IHRoZSBNU0l4IGJhciBpcyBv bmx5IG1hcHBlZCBhZnRlciBrZXJuZWwgYm9vdHMgb24gdGhlIGVuZHBvaW50LA0KPiBjb3VsZCBp dCBiZSB0b28gbGF0ZT8NCj4gDQo+IERvIHdlIG5lZWQgdG8gdHJpZ2dlciByZS1lbnVtZXJhdGlv biBvZiB0aGUgUENJIGJ1cyBmcm9tIGhvc3Qgc2lkZSB3aGVuIHdvcmtpbmcgd2l0aCB0aGlzIGFz IGFuIGVuZHBvaW50Pw0KSXQgZGVwZW5kcyBvbiBob3cgeW91IGFyZSB1c2luZyBpdC4gIFBGMCBp cyBhbHdheXMgZW5hYmxlZCBpbiB0aGUgY2FkZW5jZSBIVywgc28gd2lsbCBiZSBlbnVtZXJhdGVk IGF0IGJvb3QsDQphcyBsb25nIGFzIHRoZSBFUCBIVyBpcyBvdXQgb2YgcmVzZXQgYW5kIFBIWSBp cyBlbmFibGVkLg0KVGhlIFBDSWUgRVAgaGFyZHdhcmUgY2FuIGJlIGluaXRpYWxpemVkIHNvIHRo YXQgQkFScyBhcmUgZW5hYmxlZCBieSBkZWZhdWx0LCBiZWZvcmUgdGhlIGtlcm5lbCBib290cyBv biB0aGUNCmVuZHBvaW50LCBhbmQgc28gdGhleSB3aWxsIGJlIGZvdW5kIGFuZCBtYXBwZWQgZHVy aW5nIHRoZSBpbml0aWFsIGVudW1lcmF0aW9uIGFuZCB5b3UgZG9uJ3QgbmVlZCB0bw0KcmUtZW51 bWVyYXRlLiAgVGhlIE1TSS1YIHZlY3RvcnMgY2FuJ3QgYmUgd3JpdHRlbiB0byB0aGUgQkFSIHVu dGlsIHRoZSBFUCBrZXJuZWwgaGFzIGJvb3RlZCBhbmQgdGhlIEVQIGRyaXZlcg0KaGFzIG1hcHBl ZCB0aGUgQkFSIHRvIGxvY2FsIEVQIG1lbW9yeSB0aG91Z2ggKHVubGVzcyAgeW91IGFsc28gY29u ZmlndXJlIHRoaXMgaW4gdGhlIFBDSWUgRVAgaGFyZHdhcmUsIG9yIGluIA0KRVAgcHJlLWJvb3Qs IGJ1dCBpbiB0aGF0IGNhc2UgeW91IGFyZSBwcm9iYWJseSBub3QgdXNpbmcgdGhlIEVQIGRyaXZl ciBmcmFtZXdvcmsuKQ0KDQpUaGUgRVAgZHJpdmVyIGZyYW1ld29yayBkb2VzLCBpbiBteSB1bmRl cnN0YW5kaW5nLCBnZW5lcmFsbHkgZXhwZWN0IHJlLWVudW1lcmF0aW9uIGFmdGVyIHRoZQ0KRVAg a2VybmVsIGhhcyBib290ZWQgYW5kIHRoZSBkcml2ZXIgaGFzIGJlZW4gaW5pdGlhbGl6ZWQsIHNp bmNlIGl0IGFsbG93cyBjb25maWd1cmF0aW9uIG9mIGRldmljZSBJRCwgQkFSDQpzaXplcyBldGMu LCBhbmQgaWYgeW91IGNoYW5nZSBhbnkgb2YgdGhlc2UgZnJvbSB0aGUgSFcgZGVmYXVsdHMgYXQg Ym9vdCB5b3Ugd2lsbCBuZWVkIHRvIHJlLWVudW1lcmF0ZS4NCg0KQWxsIHRlc3RzIEkgaGF2ZSBk b25lIGZvciB0aGUgRVAgZHJpdmVyIGhhdmUgYmVlbiB3aXRob3V0IEJJT1MgZW51bWVyYXRpb24s IGFuZCB0cmlnZ2VyaW5nIHJlLWVudW1lcmF0aW9uDQphZnRlciBpbml0aWFsaXppbmcgdGhlIEJB UiBzaXplcyBldGMuIHZpYSB0aGUgRVAgZHJpdmVyDQoNClJlZ2FyZHMsDQpBbGFuDQoNCg== ^ permalink raw reply [flat|nested] 6+ messages in thread
[parent not found: <CA+Kvs9m=jECCcy6RCrtKvJOAwt5Fr8XFFkkijMy3MFe9trav5g@mail.gmail.com>]
* Re: [PATCH v2 0/5] Add MSI-X support for cadence EP driver [not found] ` <CA+Kvs9m=jECCcy6RCrtKvJOAwt5Fr8XFFkkijMy3MFe9trav5g@mail.gmail.com> @ 2018-08-17 4:09 ` Ramon Fried 2018-08-17 8:32 ` Alan Douglas 0 siblings, 1 reply; 6+ messages in thread From: Ramon Fried @ 2018-08-17 4:09 UTC (permalink / raw) To: Alan Douglas Cc: Bjorn Helgaas, kishon, lorenzo.pieralisi, linux-pci, gustavo.pimentel, cyrille.pitchen, stelford On Fri, Aug 17, 2018 at 7:05 AM Ramon Fried <ramon.fried@gmail.com> wrote: > > > > On Thu, Aug 16, 2018 at 5:28 PM Alan Douglas <adouglas@cadence.com> wrote: >> >> Hi Ramon, >> >> On 15 August 2018 17:56, Ramon Fried wrote: >> > On August 15, 2018 4:46:21 PM GMT+03:00, Alan Douglas <adouglas@cadence.com> wrote: >> > >The patch implements MSI-X support in the cadence endpoint driver. >> > > >> > >This patch depends on on Gustavo Pimentel's patch series adding MSI-X >> > >support for EP ("Add MSI-X support on pcitest tool") >> > > >> > >It also adds fixes for MSI issues discovered during testing of MSI-X >> > > - Use AXI region 0 for interrupt signalling >> > > - Write MSI and MSI-X with 32bit value rather than 16bit >> > > - Check for masking before sending MSI or MSI-X >> > > - Check link is up before sending IRQ >> > > >> > Hi. >> > AFAIK the BIOS allocates physical memory for the bars. Assuming that the MSIx bar is only mapped after kernel boots on the endpoint, >> > could it be too late? >> > >> > Do we need to trigger re-enumeration of the PCI bus from host side when working with this as an endpoint? >> It depends on how you are using it. PF0 is always enabled in the cadence HW, so will be enumerated at boot, >> as long as the EP HW is out of reset and PHY is enabled. >> The PCIe EP hardware can be initialized so that BARs are enabled by default, before the kernel boots on the >> endpoint, and so they will be found and mapped during the initial enumeration and you don't need to >> re-enumerate. The MSI-X vectors can't be written to the BAR until the EP kernel has booted and the EP driver >> has mapped the BAR to local EP memory though (unless you also configure this in the PCIe EP hardware, or in >> EP pre-boot, but in that case you are probably not using the EP driver framework.) >> >> The EP driver framework does, in my understanding, generally expect re-enumeration after the >> EP kernel has booted and the driver has been initialized, since it allows configuration of device ID, BAR >> sizes etc., and if you change any of these from the HW defaults at boot you will need to re-enumerate. >> This basically means that this driver is for hobbyist / enthusiast, you can't base a real product expecting re-enumeration of the bus. right ? > >> All tests I have done for the EP driver have been without BIOS enumeration, and triggering re-enumeration >> after initializing the BAR sizes etc. via the EP driver >> >> Regards, >> Alan >> ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v2 0/5] Add MSI-X support for cadence EP driver 2018-08-17 4:09 ` Ramon Fried @ 2018-08-17 8:32 ` Alan Douglas 2018-08-17 8:52 ` Ramon Fried 0 siblings, 1 reply; 6+ messages in thread From: Alan Douglas @ 2018-08-17 8:32 UTC (permalink / raw) To: Ramon Fried Cc: Bjorn Helgaas, kishon@ti.com, lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org, gustavo.pimentel@synopsys.com, cyrille.pitchen@bootlin.com, Scott Telford SGkgUmFtb24sDQoNCk9uIDE3IEF1Z3VzdCAyMDE4IDA1OjA5LCBSYW1vbiBGcmllZCB3cm90ZToN Cj4gT24gRnJpLCBBdWcgMTcsIDIwMTggYXQgNzowNSBBTSBSYW1vbiBGcmllZCA8cmFtb24uZnJp ZWRAZ21haWwuY29tPiB3cm90ZToNCj4gPiBPbiBUaHUsIEF1ZyAxNiwgMjAxOCBhdCA1OjI4IFBN IEFsYW4gRG91Z2xhcyA8YWRvdWdsYXNAY2FkZW5jZS5jb20+IHdyb3RlOg0KPiA+PiBPbiAxNSBB dWd1c3QgMjAxOCAxNzo1NiwgUmFtb24gRnJpZWQgd3JvdGU6DQo+ID4+ID4gT24gQXVndXN0IDE1 LCAyMDE4IDQ6NDY6MjEgUE0gR01UKzAzOjAwLCBBbGFuIERvdWdsYXMgPGFkb3VnbGFzQGNhZGVu Y2UuY29tPiB3cm90ZToNCj4gPj4gPiA+VGhlIHBhdGNoIGltcGxlbWVudHMgTVNJLVggc3VwcG9y dCBpbiB0aGUgY2FkZW5jZSBlbmRwb2ludCBkcml2ZXIuDQo+ID4+ID4gPg0KPiA+PiA+ID5UaGlz IHBhdGNoIGRlcGVuZHMgb24gb24gR3VzdGF2byBQaW1lbnRlbCdzIHBhdGNoIHNlcmllcyBhZGRp bmcgTVNJLVgNCj4gPj4gPiA+c3VwcG9ydCBmb3IgRVAgKCJBZGQgTVNJLVggc3VwcG9ydCBvbiBw Y2l0ZXN0IHRvb2wiKQ0KPiA+PiA+ID4NCj4gPj4gPiA+SXQgYWxzbyBhZGRzIGZpeGVzIGZvciBN U0kgaXNzdWVzIGRpc2NvdmVyZWQgZHVyaW5nIHRlc3Rpbmcgb2YgTVNJLVgNCj4gPj4gPiA+ICAt IFVzZSBBWEkgcmVnaW9uIDAgZm9yIGludGVycnVwdCBzaWduYWxsaW5nDQo+ID4+ID4gPiAgLSBX cml0ZSBNU0kgYW5kIE1TSS1YIHdpdGggMzJiaXQgdmFsdWUgcmF0aGVyIHRoYW4gMTZiaXQNCj4g Pj4gPiA+ICAtIENoZWNrIGZvciBtYXNraW5nIGJlZm9yZSBzZW5kaW5nIE1TSSBvciBNU0ktWA0K PiA+PiA+ID4gIC0gQ2hlY2sgbGluayBpcyB1cCBiZWZvcmUgc2VuZGluZyBJUlENCj4gPj4gPiA+ DQo+ID4+ID4gSGkuDQo+ID4+ID4gQUZBSUsgdGhlIEJJT1MgYWxsb2NhdGVzIHBoeXNpY2FsIG1l bW9yeSBmb3IgdGhlIGJhcnMuIEFzc3VtaW5nIHRoYXQgdGhlIE1TSXggYmFyIGlzIG9ubHkgbWFw cGVkIGFmdGVyIGtlcm5lbCBib290cyBvbiB0aGUNCj4gZW5kcG9pbnQsDQo+ID4+ID4gY291bGQg aXQgYmUgdG9vIGxhdGU/DQo+ID4+ID4NCj4gPj4gPiBEbyB3ZSBuZWVkIHRvIHRyaWdnZXIgcmUt ZW51bWVyYXRpb24gb2YgdGhlIFBDSSBidXMgZnJvbSBob3N0IHNpZGUgd2hlbiB3b3JraW5nIHdp dGggdGhpcyBhcyBhbiBlbmRwb2ludD8NCj4gPj4gSXQgZGVwZW5kcyBvbiBob3cgeW91IGFyZSB1 c2luZyBpdC4gIFBGMCBpcyBhbHdheXMgZW5hYmxlZCBpbiB0aGUgY2FkZW5jZSBIVywgc28gd2ls bCBiZSBlbnVtZXJhdGVkIGF0IGJvb3QsDQo+ID4+IGFzIGxvbmcgYXMgdGhlIEVQIEhXIGlzIG91 dCBvZiByZXNldCBhbmQgUEhZIGlzIGVuYWJsZWQuDQo+ID4+IFRoZSBQQ0llIEVQIGhhcmR3YXJl IGNhbiBiZSBpbml0aWFsaXplZCBzbyB0aGF0IEJBUnMgYXJlIGVuYWJsZWQgYnkgZGVmYXVsdCwg YmVmb3JlIHRoZSBrZXJuZWwgYm9vdHMgb24gdGhlDQo+ID4+IGVuZHBvaW50LCBhbmQgc28gdGhl eSB3aWxsIGJlIGZvdW5kIGFuZCBtYXBwZWQgZHVyaW5nIHRoZSBpbml0aWFsIGVudW1lcmF0aW9u IGFuZCB5b3UgZG9uJ3QgbmVlZCB0bw0KPiA+PiByZS1lbnVtZXJhdGUuICBUaGUgTVNJLVggdmVj dG9ycyBjYW4ndCBiZSB3cml0dGVuIHRvIHRoZSBCQVIgdW50aWwgdGhlIEVQIGtlcm5lbCBoYXMg Ym9vdGVkIGFuZCB0aGUgRVAgZHJpdmVyDQo+ID4+IGhhcyBtYXBwZWQgdGhlIEJBUiB0byBsb2Nh bCBFUCBtZW1vcnkgdGhvdWdoICh1bmxlc3MgIHlvdSBhbHNvIGNvbmZpZ3VyZSB0aGlzIGluIHRo ZSBQQ0llIEVQIGhhcmR3YXJlLCBvciBpbg0KPiA+PiBFUCBwcmUtYm9vdCwgYnV0IGluIHRoYXQg Y2FzZSB5b3UgYXJlIHByb2JhYmx5IG5vdCB1c2luZyB0aGUgRVAgZHJpdmVyIGZyYW1ld29yay4p DQo+ID4+DQo+ID4+IFRoZSBFUCBkcml2ZXIgZnJhbWV3b3JrIGRvZXMsIGluIG15IHVuZGVyc3Rh bmRpbmcsIGdlbmVyYWxseSBleHBlY3QgcmUtZW51bWVyYXRpb24gYWZ0ZXIgdGhlDQo+ID4+IEVQ IGtlcm5lbCBoYXMgYm9vdGVkIGFuZCB0aGUgZHJpdmVyIGhhcyBiZWVuIGluaXRpYWxpemVkLCBz aW5jZSBpdCBhbGxvd3MgY29uZmlndXJhdGlvbiBvZiBkZXZpY2UgSUQsIEJBUg0KPiA+PiBzaXpl cyBldGMuLCBhbmQgaWYgeW91IGNoYW5nZSBhbnkgb2YgdGhlc2UgZnJvbSB0aGUgSFcgZGVmYXVs dHMgYXQgYm9vdCB5b3Ugd2lsbCBuZWVkIHRvIHJlLWVudW1lcmF0ZS4NCj4gPj4NCj4gVGhpcyBi YXNpY2FsbHkgbWVhbnMgdGhhdCB0aGlzIGRyaXZlciBpcyBmb3IgaG9iYnlpc3QgLyBlbnRodXNp YXN0LA0KPiB5b3UgY2FuJ3QgYmFzZSBhIHJlYWwgcHJvZHVjdCBleHBlY3RpbmcNCj4gcmUtZW51 bWVyYXRpb24gb2YgdGhlIGJ1cy4gcmlnaHQgPw0KSXQgZGVwZW5kcyB3aGF0IHlvdSBtZWFuIGJ5 IGEgcmVhbCBwcm9kdWN0LCBidXQgeWVzIGl0J3Mgbm90IGludGVuZGVkIGZvciB1c2UgaW4gYSB0 eXBpY2FsIFBDSWUgZGV2aWNlLg0KVGhlcmUgYXJlIGEgd2lkZSB2YXJpZXR5IG9mIHVzZSBjYXNl cyBmb3IgdGhlIEVQIGRyaXZlciBmcmFtZXdvcmssIG5vdCBuZWNlc3NhcmlseSBob2JieWlzdC9l bnRodXNpYXN0Lg0KVGhlIGRvY3VtZW50YXRpb24gaGVyZTogaHR0cHM6Ly93d3cua2VybmVsLm9y Zy9kb2MvRG9jdW1lbnRhdGlvbi9QQ0kvZW5kcG9pbnQvcGNpLWVuZHBvaW50LnR4dA0KbWVudGlv bnMgdGVzdGluZyBvciB2YWxpZGF0aW9uLCBjby1wcm9jZXNzb3IgYWNjZWxlcmF0b3IsIGV0Yy4g YXMgcG9zc2libGUgdXNlIGNhc2VzLg0KDQpSZWdhcmRzLA0KQWxhbg0K ^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v2 0/5] Add MSI-X support for cadence EP driver 2018-08-17 8:32 ` Alan Douglas @ 2018-08-17 8:52 ` Ramon Fried 0 siblings, 0 replies; 6+ messages in thread From: Ramon Fried @ 2018-08-17 8:52 UTC (permalink / raw) To: Alan Douglas Cc: Bjorn Helgaas, kishon@ti.com, lorenzo.pieralisi@arm.com, linux-pci@vger.kernel.org, gustavo.pimentel@synopsys.com, cyrille.pitchen@bootlin.com, Scott Telford On August 17, 2018 11:32:03 AM GMT+03:00, Alan Douglas <adouglas@cadence=2E= com> wrote: >Hi Ramon, > >On 17 August 2018 05:09, Ramon Fried wrote: >> On Fri, Aug 17, 2018 at 7:05 AM Ramon Fried <ramon=2Efried@gmail=2Ecom> >wrote: >> > On Thu, Aug 16, 2018 at 5:28 PM Alan Douglas <adouglas@cadence=2Ecom> >wrote: >> >> On 15 August 2018 17:56, Ramon Fried wrote: >> >> > On August 15, 2018 4:46:21 PM GMT+03:00, Alan Douglas ><adouglas@cadence=2Ecom> wrote: >> >> > >The patch implements MSI-X support in the cadence endpoint >driver=2E >> >> > > >> >> > >This patch depends on on Gustavo Pimentel's patch series adding >MSI-X >> >> > >support for EP ("Add MSI-X support on pcitest tool") >> >> > > >> >> > >It also adds fixes for MSI issues discovered during testing of >MSI-X >> >> > > - Use AXI region 0 for interrupt signalling >> >> > > - Write MSI and MSI-X with 32bit value rather than 16bit >> >> > > - Check for masking before sending MSI or MSI-X >> >> > > - Check link is up before sending IRQ >> >> > > >> >> > Hi=2E >> >> > AFAIK the BIOS allocates physical memory for the bars=2E Assuming >that the MSIx bar is only mapped after kernel boots on the >> endpoint, >> >> > could it be too late? >> >> > >> >> > Do we need to trigger re-enumeration of the PCI bus from host >side when working with this as an endpoint? >> >> It depends on how you are using it=2E PF0 is always enabled in the >cadence HW, so will be enumerated at boot, >> >> as long as the EP HW is out of reset and PHY is enabled=2E >> >> The PCIe EP hardware can be initialized so that BARs are enabled >by default, before the kernel boots on the >> >> endpoint, and so they will be found and mapped during the initial >enumeration and you don't need to >> >> re-enumerate=2E The MSI-X vectors can't be written to the BAR until >the EP kernel has booted and the EP driver >> >> has mapped the BAR to local EP memory though (unless you also >configure this in the PCIe EP hardware, or in >> >> EP pre-boot, but in that case you are probably not using the EP >driver framework=2E) >> >> >> >> The EP driver framework does, in my understanding, generally >expect re-enumeration after the >> >> EP kernel has booted and the driver has been initialized, since it >allows configuration of device ID, BAR >> >> sizes etc=2E, and if you change any of these from the HW defaults at >boot you will need to re-enumerate=2E >> >> >> This basically means that this driver is for hobbyist / enthusiast, >> you can't base a real product expecting >> re-enumeration of the bus=2E right ? >It depends what you mean by a real product, but yes it's not intended >for use in a typical PCIe device=2E >There are a wide variety of use cases for the EP driver framework, not >necessarily hobbyist/enthusiast=2E >The documentation here: >https://www=2Ekernel=2Eorg/doc/Documentation/PCI/endpoint/pci-endpoint=2E= txt >mentions testing or validation, co-processor accelerator, etc=2E as >possible use cases=2E > Thanks Alan=2E=20 >Regards, >Alan --=20 Sent from my Android device with K-9 Mail=2E Please excuse my brevity=2E ^ permalink raw reply [flat|nested] 6+ messages in thread
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Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2018-08-15 13:46 [PATCH v2 0/5] Add MSI-X support for cadence EP driver Alan Douglas
2018-08-15 16:55 ` Ramon Fried
2018-08-16 14:28 ` Alan Douglas
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2018-08-17 4:09 ` Ramon Fried
2018-08-17 8:32 ` Alan Douglas
2018-08-17 8:52 ` Ramon Fried
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