Re: [PATCH V6 2/3] PCI: dwc: Cleanup DBI read and write APIs

[Vidya Sagar <vidyas@nvidia.com>]

On 6/22/2019 10:56 AM, Jingoo Han wrote:
> On 6/21/19, 8:10 PM, Vidya Sagar wrote:
>>
>> Cleanup DBI read and write APIs by removing "__" (underscore) from their
>> names as there are no no-underscore versions and the underscore versions
>> are already doing what no-underscore versions typically do. It also removes
>> passing dbi/dbi2 base address as one of the arguments as the same can be
>> derived with in read and write APIs.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> ---
>> Changes from v5:
>> * Removed passing base address as one of the arguments as the same can be derived within
>>    the API itself.
>> * Modified ATU read/write APIs to call dw_pcie_{write/read}() API
> 
> Unlike previous patches (v1~v5), you modified ATU read/write APIs from v6.
> Why do you change ATU read/write APIs to call dw_pcie_{write/read}() API???
> It is not clean-up, but function change. Please add the reason to the commit message.
> 
> Best regards,
> Jingoo Han
Reason is that, now dbi/dbi2 APIs don't take base address offset as one of the input arguments
instead, those APIs derive that inside the API itself. So, for ATU read/write DBI read/write
APIs can be used directly and hence I called dw_pcie_{write/read}() API directly. But, taking a
second look at it, it may work for Tegra, but, may not for other implementations where accessing
DBI space is not a simple read/write to DBI base + offset. Let me address address that too in
next patch.

Thanks,
Vidya Sagar

> 
>>
>> Changes from v4:
>> * This is a new patch in this series
>>
>>   drivers/pci/controller/dwc/pcie-designware.c | 28 ++++++-------
>>   drivers/pci/controller/dwc/pcie-designware.h | 43 ++++++++++++--------
>>   2 files changed, 37 insertions(+), 34 deletions(-)
> 
> .....
> 
>>   static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)
>>   {
>> -	__dw_pcie_write_dbi(pci, pci->atu_base, reg, 0x4, val);
>> +	int ret;
>> +
>> +	ret = dw_pcie_write(pci->atu_base + reg, 0x4, val);
>> +	if (ret)
>> +		dev_err(pci->dev, "write ATU address failed\n");
>>   }
>>   
>>   static inline u32 dw_pcie_readl_atu(struct dw_pcie *pci, u32 reg)
>>   {
>> -	return __dw_pcie_read_dbi(pci, pci->atu_base, reg, 0x4);
>> +	int ret;
>> +	u32 val;
>> +
>> +	ret = dw_pcie_read(pci->atu_base + reg, 0x4, &val);
>> +	if (ret)
>> +		dev_err(pci->dev, "Read ATU address failed\n");
>> +
>> +	return val;
>>   }
>>   
>>   static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)
>> -- 
>> 2.17.1
>