From: Dan Williams <dan.j.williams@intel.com>
To: Dan Williams <dan.j.williams@intel.com>, <ira.weiny@intel.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ira Weiny <ira.weiny@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
"Dave Jiang" <dave.jiang@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-cxl@vger.kernel.org>,
<linux-pci@vger.kernel.org>
Subject: RE: [PATCH V11 5/8] cxl/port: Read CDAT table
Date: Tue, 21 Jun 2022 12:10:03 -0700 [thread overview]
Message-ID: <62b2178bdcf5d_89207294ac@dwillia2-xfh.notmuch> (raw)
In-Reply-To: <62ad1fb69d742_8920729490@dwillia2-xfh.notmuch>
Dan Williams wrote:
> ira.weiny@ wrote:
> > From: Ira Weiny <ira.weiny@intel.com>
[..]
> > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> > index c4c99ff7b55e..84dc82f7dff0 100644
> > --- a/drivers/cxl/core/pci.c
> > +++ b/drivers/cxl/core/pci.c
> > @@ -4,10 +4,12 @@
> > #include <linux/device.h>
> > #include <linux/delay.h>
> > #include <linux/pci.h>
> > +#include <linux/pci-doe.h>
> > #include <cxlpci.h>
> > #include <cxlmem.h>
> > #include <cxl.h>
> > #include "core.h"
> > +#include "cdat.h"
> >
> > /**
> > * DOC: cxl core pci
> > @@ -458,3 +460,173 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm)
> > return 0;
> > }
> > EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);
> > +
> > +static struct pci_doe_mb *find_cdat_mb(struct device *uport)
> > +{
> > + struct cxl_memdev *cxlmd;
> > + struct cxl_dev_state *cxlds;
> > + int i;
> > +
> > + if (!is_cxl_memdev(uport))
> > + return NULL;
> > +
> > + cxlmd = to_cxl_memdev(uport);
> > + cxlds = cxlmd->cxlds;
>
> This feels stuck between 2 worlds. Either cxl_port_probe() needs to do
> the enumeration, or the attribute needs to move to be memdev relative.
> Given that CXL switches are going to also have CDAT data, then the
> former path needs to happen. Yes, cxl_pci still needs to do the vector
> allocation, but it does not need to do the PCI DOE probing.
It is really the interrupt setup that makes this an awkward fit all
around. The PCI core knows how to handle capabilities with interrupts,
but only for PCIe port services. DOE is both a PCIe port service *and*
and "endpoint service" like VPD (pci_vpd_init()). The more I think about
this the closer I get to the recommendation from Lukas which is that
DOE is more like pci_vpd_init() than pci_aer_init(), or a custom
enabling per driver.
If the DOE enumeration moves to a sub-function of
pci_init_capabilities() then the cxl_pci and/or cxl_port drivers just
look those up and use them. The DOE instances would remain in polled
mode unless and until a PCI driver added interrupt support late. In
other words, DOE can follow the VPD init model as long as interrupts are
not involved, and if interrupts are desired it requires late allocation
of IRQ vectors.
next prev parent reply other threads:[~2022-06-21 19:10 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-10 20:22 [PATCH V11 0/8] CXL: Read CDAT and DSMAS data ira.weiny
2022-06-10 20:22 ` [PATCH V11 1/8] PCI: Add vendor ID for the PCI SIG ira.weiny
2022-06-10 20:22 ` [PATCH V11 2/8] PCI: Replace magic constant for PCI Sig Vendor ID ira.weiny
2022-06-10 20:22 ` [PATCH V11 3/8] PCI: Create PCI library functions in support of DOE mailboxes ira.weiny
2022-06-14 3:53 ` Li, Ming
2022-06-15 4:18 ` Ira Weiny
2022-06-17 22:40 ` Bjorn Helgaas
2022-06-18 16:39 ` Bjorn Helgaas
2022-06-22 16:46 ` Ira Weiny
2022-06-20 9:24 ` Jonathan Cameron
2022-06-22 23:06 ` Ira Weiny
2022-06-22 16:38 ` Ira Weiny
2022-06-17 22:56 ` Dan Williams
2022-06-20 10:23 ` Jonathan Cameron
2022-06-22 22:57 ` Ira Weiny
2022-06-23 18:03 ` Dan Williams
2022-06-22 22:37 ` Ira Weiny
2022-06-22 22:45 ` Ira Weiny
2022-06-22 22:57 ` Dan Williams
2022-06-23 0:25 ` Ira Weiny
2022-06-23 10:24 ` Jonathan Cameron
2022-06-23 18:14 ` Dan Williams
2022-06-23 18:07 ` Dan Williams
2022-06-10 20:22 ` [PATCH V11 4/8] cxl/pci: Create PCI DOE mailbox's for memory devices ira.weiny
2022-06-17 20:40 ` [PATCH v11 " Davidlohr Bueso
2022-06-17 20:51 ` Davidlohr Bueso
2022-06-21 18:24 ` Ira Weiny
2022-06-17 23:44 ` [PATCH V11 " Dan Williams
2022-06-21 18:29 ` Ira Weiny
2022-06-22 23:18 ` Ira Weiny
2022-06-21 20:37 ` Bjorn Helgaas
2022-06-10 20:22 ` [PATCH V11 5/8] cxl/port: Read CDAT table ira.weiny
2022-06-18 0:43 ` Dan Williams
2022-06-21 19:10 ` Dan Williams [this message]
2022-06-21 19:34 ` Lukas Wunner
2022-06-21 19:41 ` Dan Williams
2022-06-21 20:38 ` Ira Weiny
2022-06-21 21:14 ` Ira Weiny
2022-06-21 21:48 ` Dan Williams
2022-06-28 3:24 ` Ira Weiny
2022-06-10 20:22 ` [PATCH V11 6/8] cxl/port: Introduce cxl_cdat_valid() ira.weiny
2022-06-10 20:22 ` [PATCH V11 7/8] cxl/port: Retry reading CDAT on failure ira.weiny
2022-06-28 3:32 ` Alison Schofield
2022-06-10 20:22 ` [PATCH V11 8/8] cxl/port: Parse out DSMAS data from CDAT table ira.weiny
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