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Mon, 22 Dec 2025 20:35:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IHkRpDAVO328ItJj7fT7qtlRC67hmAxEdch9oNkhrGUH1YoHfKdi+X2vAQNg/JUJLFGl/a7+Q== X-Received: by 2002:a05:6a00:278a:b0:79a:fd01:dfa9 with SMTP id d2e1a72fcca58-7ff64215308mr13201695b3a.6.1766464538886; Mon, 22 Dec 2025 20:35:38 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7ff7a843ee4sm12220907b3a.10.2025.12.22.20.35.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Dec 2025 20:35:38 -0800 (PST) Message-ID: <63321b7d-74a7-448f-ab20-08cc771beb5d@oss.qualcomm.com> Date: Tue, 23 Dec 2025 10:05:33 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] PCI: dwc: ep: Cache MSI outbound iATU mapping To: Shawn Lin , Niklas Cassel Cc: Manivannan Sadhasivam , Jingoo Han , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Frank Li , Damien Le Moal , Koichiro Den , linux-pci@vger.kernel.org References: <20251210071358.2267494-2-cassel@kernel.org> <8e00bd1c-29ae-43fd-90e8-ea0943cb02b6@oss.qualcomm.com> <3b34aa66-a418-4f6b-930a-0728d87d79b6@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIzMDAzNiBTYWx0ZWRfX7139lz8f8jwa 2yjK3xgEd1tHlLl1//lUhC+RAY+UuosPYbzSQvJsR79/FZSc8U5B5bXExryHxPVQrbLMEj1cO2M /LHqcTt7itllPMTP+dDfR1NfA1xEmAIArSmhXMWMo2wuTgTtPZfX1ByGS1UccPTIglWjWJxwyh4 HekIvQ7O78iFBk5kyyP1ArrCC5YYW9mHeA45vXFbTXnFl5SwdLbeGRT6uWV4lKbh7RUI9ZPFuOu R/sgnNbzFVpw5nKXQWyFJcyCkNv1x93XzpBcKknB65Z5P4wRETUHdexGbeQl+mRqV7Wryxnvuac C5r8QG/Fze4WC5DbFeURd6f8nSFSWAEJf7m9vwDOtETsetzZWkl+Wju+d5sUEsMynUlaCbkWyjs RJOvv5CsXfMOcZKGo1WUotzjcMoEmwS7/rv6yzA0iJ0l8EJ7xjHYlzBtZE4Edm7pcVU/li96Mi6 QCVS2Ah1rTaCHK4damw== X-Authority-Analysis: v=2.4 cv=Zb0Q98VA c=1 sm=1 tr=0 ts=694a1c1c cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=0o6G4FUzGTm6UKix0egA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: IGOJ3SxxcF9t-y0vFcuBzOLFUcjq2Nc1 X-Proofpoint-GUID: IGOJ3SxxcF9t-y0vFcuBzOLFUcjq2Nc1 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-23_01,2025-12-22_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 phishscore=0 spamscore=0 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512230036 On 12/23/2025 6:42 AM, Shawn Lin wrote: > 在 2025/12/22 星期一 21:00, Niklas Cassel 写道: >> + Shawn >> >> On Mon, Dec 22, 2025 at 05:53:27PM +0530, Krishna Chaitanya Chundru >> wrote: >>> >>> >>> On 12/22/2025 4:41 PM, Niklas Cassel wrote: >>>> On Mon, Dec 22, 2025 at 03:28:30PM +0530, Manivannan Sadhasivam wrote: >>>>>> Use the MSIX doorbell method which will not use iATU at all, >>>>>> dw_pcie_ep_raise_msix_irq_doorbell(). >>>>>> >>>>> I think this is the safe bet since this feature doesn't seem like >>>>> an optional >>>>> one. >>>>> >>>>> Niklas, if you can just fix MSI in this patch and leave out MSI-X >>>>> for the vendor >>>>> drivers to transition to doorbell, I'm OK to merge it. Otherwise, >>>>> I don't know >>>>> how you can reliably fix MSI-X generation with AXI slave interface. >>>> FWIW, I did try to simply change: >>>> >>>> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c >>>> b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >>>> index 8f2cc1ef25e3..00770f9786e3 100644 >>>> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c >>>> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c >>>> @@ -319,7 +319,8 @@ static int rockchip_pcie_raise_irq(struct >>>> dw_pcie_ep *ep, u8 func_no, >>>>           case PCI_IRQ_MSI: >>>>                   return dw_pcie_ep_raise_msi_irq(ep, func_no, >>>> interrupt_num); >>>>           case PCI_IRQ_MSIX: >>>> -               return dw_pcie_ep_raise_msix_irq(ep, func_no, >>>> interrupt_num); >>>> +               return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no, >>>> + interrupt_num); >>>>           default: >>>>                   dev_err(pci->dev, "UNKNOWN IRQ type\n"); >>>>           } >>>> >>>> >>>> For the pcie-dw-rockchip driver, but it is not working: >>>> [  130.042849] nvme nvme0: I/O tag 0 (1000) QID 0 timeout, >>>> completion polled >>>> >>>> Without this change, things work. >>>> >>>> Perhaps this feature is not an optional one, but at least we will >>>> require >>>> more changes than a simple one liner. >>> Hi Niklas, >>> >>> It should be automatic only, no extra configurations should be >>> required, I believe your >>> HW doesn't support this feature, from spec 6..0a, sec 3.9.1.3 >>> iMSIX-TX: Integrated MSI-X Transmit (USP) >>> I believe your HW is not generated with MSIX_TABLE_EN =1. In that >>> case you can't use this feature. >> >> Looking at the RK3588 TRM, it does have register: >> USP_PCIE_PL_MSIX_DOORBELL_OFF >> Address: Operational Base + offset (0x0248) >> >> Port Logic registers start at offset 0x700 on this SoC, >> so 0x700 + 0x248 == 0x948, which matches: >> drivers/pci/controller/dwc/pcie-designware.h:#define >> PCIE_MSIX_DOORBELL         0x948 >> >> I don't think the TRM would include this register if the >> DWC coere was not generated with MSIX_TABLE_EN=1. >> > > I checked the IP configurtion parameters for RK3588 DM controller for > sure, it sets MSIX_TABLE_EN=1. > > Looking into dw_pcie_ep_raise_msix_irq_doorbell(), it doesn't seem to > match the dwc databook. No matter for non-AXI mode or AXI access mode, > shouldn't we need to generate a MSI-X table RAM with > data/address/vector/TC in advanced? Am I missing anything because I > didn't look The MSI-X table will updated automatically when host updates the MSI-X table, when MSI-X is enabled by host. - Krishna Chaitanya. > too much regarding to the EPC side? > >> Shawn, any suggestions? >> For full thread, see: >> https://lore.kernel.org/linux-pci/3b34aa66-a418-4f6b-930a-0728d87d79b6@oss.qualcomm.com/T/#t >> >> >> >> FWIW, Krishna Chaitanya, I did try the >> dw_pcie_ep_raise_msix_irq_doorbell() >> change above also with the pci-epf-test EPF driver, and it also >> caused the >> pci-epf-test driver to stop working. >> >> >> Kind regards, >> Niklas >> >