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From: Ira Weiny <ira.weiny@intel.com>
To: Dan Williams <dan.j.williams@intel.com>, Ira Weiny <ira.weiny@intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	"Ira Weiny" <ira.weiny@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	"Jonathan Cameron" <Jonathan.Cameron@huawei.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>,
	Steven Rostedt <rostedt@goodmis.org>,
	<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linux-acpi@vger.kernel.org>, <linux-cxl@vger.kernel.org>
Subject: RE: [PATCH v7 1/8] cxl/mem: Read, trace, and clear events on driver load
Date: Fri, 27 Jan 2023 11:45:07 -0800	[thread overview]
Message-ID: <63d429c39ecbb_7be472948f@iweiny-mobl.notmuch> (raw)
In-Reply-To: <63d31f8fbb678_ea222294a3@dwillia2-xfh.jf.intel.com.notmuch>

Dan Williams wrote:
> Ira Weiny wrote:

[snip]

> [..]
> > diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h
> > index 20ca2fe2ca8e..6898212fcb47 100644
> > --- a/drivers/cxl/core/trace.h
> > +++ b/drivers/cxl/core/trace.h
> > @@ -6,7 +6,9 @@
> >  #if !defined(_CXL_EVENTS_H) || defined(TRACE_HEADER_MULTI_READ)
> >  #define _CXL_EVENTS_H
> >  
> > +#include <asm-generic/unaligned.h>
> >  #include <cxl.h>
> > +#include <cxlmem.h>
> >  #include <linux/tracepoint.h>
> >  
> >  #define CXL_RAS_UC_CACHE_DATA_PARITY	BIT(0)
> > @@ -103,6 +105,124 @@ TRACE_EVENT(cxl_aer_correctable_error,
> >  	)
> >  );
> >  
> > +#include <linux/tracepoint.h>
> 
> missed this earlier, no need to include this again. Will drop it in my
> local tree.

Thanks!
Ira

  reply	other threads:[~2023-01-27 20:04 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-18  5:53 [PATCH v7 0/8] cxl: Process event logs Ira Weiny
2023-01-18  5:53 ` [PATCH v7 1/8] cxl/mem: Read, trace, and clear events on driver load Ira Weiny
2023-01-26 21:53   ` Dan Williams
2023-01-27  0:49   ` Dan Williams
2023-01-27 19:45     ` Ira Weiny [this message]
2023-05-05  9:47   ` Huai-Cheng
2023-05-08  2:41     ` Ira Weiny
2023-05-09 21:41   ` Dave Jiang
2023-01-18  5:53 ` [PATCH v7 2/8] cxl/mem: Wire up event interrupts ira.weiny
2023-01-26 22:00   ` Dan Williams
2023-05-09 21:42   ` Dave Jiang
     [not found]     ` <tencent_D9D9D358330CA573E23D490C6EE13E0DC105@qq.com>
2023-05-19  1:38       ` CXL memory device not created correctly Davidlohr Bueso
2023-05-19 15:10         ` Jonathan Cameron
2023-05-19 15:20         ` Ira Weiny
2023-05-19 15:37           ` Jonathan Cameron
2023-05-31  2:18           ` Luis Chamberlain
2023-06-01  3:12             ` Ira Weiny
2023-06-01  3:46               ` Davidlohr Bueso
2023-01-18  5:53 ` [PATCH v7 3/8] cxl/mem: Trace General Media Event Record Ira Weiny
2023-05-09 21:47   ` Dave Jiang
2023-01-18  5:53 ` [PATCH v7 4/8] cxl/mem: Trace DRAM " Ira Weiny
2023-05-09 21:48   ` Dave Jiang
2023-01-18  5:53 ` [PATCH v7 5/8] cxl/mem: Trace Memory Module " Ira Weiny
2023-05-09 21:52   ` Dave Jiang
2023-01-18  5:53 ` [PATCH v7 6/8] cxl/test: Add generic mock events Ira Weiny
2023-05-09 22:03   ` Dave Jiang
2023-01-18  5:53 ` [PATCH v7 7/8] cxl/test: Add specific events Ira Weiny
2023-05-09 22:08   ` Dave Jiang
2023-01-18  5:53 ` [PATCH v7 8/8] cxl/test: Simulate event log overflow Ira Weiny
2023-05-09 22:31   ` Dave Jiang

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