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From: Philipp Zabel <p.zabel@pengutronix.de>
To: "Anand Moon" <linux.amoon@gmail.com>,
	"Shawn Lin" <shawn.lin@rock-chips.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Heiko Stuebner" <heiko@sntech.de>,
	"open list:PCIE DRIVER FOR ROCKCHIP" <linux-pci@vger.kernel.org>,
	"open list:PCIE DRIVER FOR ROCKCHIP"
	<linux-rockchip@lists.infradead.org>,
	"moderated list:ARM/Rockchip SoC support"
	<linux-arm-kernel@lists.infradead.org>,
	"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v6 RESET 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function
Date: Mon, 07 Oct 2024 10:43:59 +0200	[thread overview]
Message-ID: <64c560c483f09d90c788eb949890d00f3b94cc87.camel@pengutronix.de> (raw)
In-Reply-To: <20241006182445.3713-3-linux.amoon@gmail.com>

On So, 2024-10-06 at 23:54 +0530, Anand Moon wrote:
> Refactor the reset control handling in the Rockchip PCIe driver,
> introducing a more robust and efficient method for assert and
> deassert reset controller using reset_control_bulk*() API. Using the
> reset_control_bulk APIs, the reset handling for the core clocks reset
> unit becomes much simpler.
> 
> Spilt the reset controller in two groups as pre the RK3399 TRM.
> After power up, the software driver should de-assert the reset of PCIe PHY,
> then wait the PLL locked by polling the status, if PLL
> has locked, then can de-assert the rest reset simultaneously
> driver need to De-assert the reset pins simultionaly.
> 
>   PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N.
> 
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> ---
> V6: Add reason for the split of the RESET pins.
> v5: Fix the De-assert reset core as per the TRM
>     De-assert the PIPE_RESET_N/MGMT_STICKY_RESET_N/MGMT_RESET_N/RESET_N
>     simultaneously.
> v4: use dev_err_probe in error path.
> v3: Fix typo in commit message, dropped reported by.
> v2: Fix compilation error reported by Intel test robot
>     fixed checkpatch warning
> ---
>  drivers/pci/controller/pcie-rockchip.c | 151 +++++--------------------
>  drivers/pci/controller/pcie-rockchip.h |  26 +++--
>  2 files changed, 49 insertions(+), 128 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c
> index 2777ef0cb599..87daa3288a01 100644
> --- a/drivers/pci/controller/pcie-rockchip.c
> +++ b/drivers/pci/controller/pcie-rockchip.c
[...]
> @@ -69,55 +69,23 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
>  	if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
>  		rockchip->link_gen = 2;
>  
> -	rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
> -	rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
> -	rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev,
> -	rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
> -	rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
> +	err = devm_reset_control_bulk_get_optional_exclusive(dev,
[...]


Why are the reset controls optional now? The commit message doesn't
mention this change.

regards
Philipp

  reply	other threads:[~2024-10-07  8:44 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-06 18:24 [PATCH v6 RESET 0/3] PCIe RK3399 clock and reset using new helper functions Anand Moon
2024-10-06 18:24 ` [PATCH v6 RESET 1/3] PCI: rockchip: Simplify clock handling by using clk_bulk*() function Anand Moon
2024-10-09 17:19   ` Dan Carpenter
2024-10-06 18:24 ` [PATCH v6 RESET 2/3] PCI: rockchip: Simplify reset control handling by using reset_control_bulk*() function Anand Moon
2024-10-07  8:43   ` Philipp Zabel [this message]
2024-10-07  9:09     ` Anand Moon
2024-10-06 18:24 ` [PATCH v6 RESET 3/3] PCI: rockchip: Refactor rockchip_pcie_disable_clocks() function signature Anand Moon

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