From: Dan Williams <dan.j.williams@intel.com>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-cxl@vger.kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>, <oohall@gmail.com>,
Lukas Wunner <lukas@wunner.de>,
Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@linux.intel.com>,
Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
Alison Schofield <alison.schofield@intel.com>,
"Vishal Verma" <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
"Ben Widawsky" <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Yazen Ghannam <yazen.ghannam@amd.com>,
Terry Bowman <terry.bowman@amd.com>,
Robert Richter <rrichter@amd.com>,
Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Subject: RE: [PATCH v2 2/3] PCI/AER: Export pcie_aer_is_native()
Date: Mon, 7 Aug 2023 20:20:27 -0700 [thread overview]
Message-ID: <64d1b47b7bd8_5ea6e2948c@dwillia2-xfh.jf.intel.com.notmuch> (raw)
In-Reply-To: <20230721214740.256602-3-Smita.KoralahalliChannabasappa@amd.com>
Smita Koralahalli wrote:
> Export and move the declaration of pcie_aer_is_native() to a common header
> file to be reused by cxl/pci module.
>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> ---
> v2:
> Fixed $SUBJECT
> ---
> drivers/pci/pcie/aer.c | 1 +
> drivers/pci/pcie/portdrv.h | 2 --
> include/linux/aer.h | 2 ++
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
> index f6c24ded134c..87d90dbda023 100644
> --- a/drivers/pci/pcie/aer.c
> +++ b/drivers/pci/pcie/aer.c
> @@ -229,6 +229,7 @@ int pcie_aer_is_native(struct pci_dev *dev)
>
> return pcie_ports_native || host->native_aer;
> }
> +EXPORT_SYMBOL_GPL(pcie_aer_is_native);
I would put this in the CXL symbol namespace since no other driver has
any business using this. Only the CXL subsystem, which is forced by the
specification to take on some PCI core work in its endpoint driver,
needs this export.
Otherwise, looks good to me.
next prev parent reply other threads:[~2023-08-08 3:21 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-21 21:47 [PATCH v2 0/3] PCI/AER, CXL: Fix appropriate _OSC check for CXL RAS Cap Smita Koralahalli
2023-07-21 21:47 ` [PATCH v2 1/3] cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers Smita Koralahalli
2023-07-22 0:18 ` Sathyanarayanan Kuppuswamy
2023-07-24 21:59 ` Smita Koralahalli
2023-08-08 3:22 ` Dan Williams
2023-07-24 12:02 ` Robert Richter
2023-08-08 3:17 ` Dan Williams
2023-08-08 19:37 ` Smita Koralahalli
2023-07-21 21:47 ` [PATCH v2 2/3] PCI/AER: Export pcie_aer_is_native() Smita Koralahalli
2023-07-24 12:42 ` Robert Richter
2023-08-08 3:20 ` Dan Williams [this message]
2023-07-21 21:47 ` [PATCH v2 3/3] cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native() Smita Koralahalli
2023-07-22 0:17 ` Sathyanarayanan Kuppuswamy
2023-07-24 12:44 ` Robert Richter
2023-08-08 3:21 ` Dan Williams
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