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Mon, 21 Sep 2026 02:15:12 -0700 (PDT) X-Received: by 2002:a17:903:468e:b0:2dd:c100:4b81 with SMTP id d9443c01a7336-2ddc1005f8cmr91843865ad.56.1789982111982; Mon, 21 Sep 2026 02:15:11 -0700 (PDT) Received: from [10.151.37.217] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33c3311ad4esm17917215eec.5.2026.09.21.02.15.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Sep 2026 02:15:11 -0700 (PDT) Message-ID: <65d9422c-d691-4b5f-b1f3-c2ae5ba5cfc8@oss.qualcomm.com> Date: Mon, 21 Sep 2026 14:45:05 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/4] phy: qcom-qmp-pcie: Split phy_ops into init/exit/reset/power_on To: Qiang Yu , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Vinod Koul , Neil Armstrong , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org References: <20260915-align_pcie_init_sequence_0916-v1-0-0b2195836f30@oss.qualcomm.com> <20260915-align_pcie_init_sequence_0916-v1-4-0b2195836f30@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-4-0b2195836f30@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIxMDEzMSBTYWx0ZWRfX39lQgf7CJ1q2 i5NgF9t/K76I1V8K0ykwSv8jeQfDtI5pGXDb3hK1BIhTr7kvm8vFmFzT51fDKH562rAoGhMcTya JAwM16hcXMwjby5F6TQfB1C8FdFjJCU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIxMDEzMSBTYWx0ZWRfXxhBGY1AiUCmD 9er0iAo7NNDVXHuFXmneqz+o5S1ZnjGuDf97SPG5OYjEhrX6tfGbsl3W8RYzhsAJzxcOL1n4eLq 7r4NVN7dLExS2WNyUc5BnLNBhYWLPgEOpKzd6OJ6gZAgs31ElDS9MXAj2mnXbpkeAEeAj51GEMt nNWn02/lQW8u1DmD/zCW+iGTrPEWfg04jpMYv43JrFxkqDt+nnqB2q+FL822fw4wo5P1ZChhuGS fzQpjGTjBg4PeKN4FDkULJQM2b7JKxAfwJbbtTz0j53OZg9cxLQh9EDvk7eMlcTysZAe9vBk9XB x1BDzEKokc+72GP3GDhiikpPP+dxCLX5d8GzLIa8oRRr4vjwUtwZOWmnhHsntoSjR8/B1goyaDU 2RZ8wqKLXWTy2uRod2/NQigiVQ1zQakDyUuGSg+vTnx+ZMTyodnJantp255J/3y1BdTiPoJ2Fey b8JzruQQBtnpiDyp1Jw== X-Proofpoint-ORIG-GUID: hSHyU4QiIDaugat5GsmgakY7jqrTZvTg X-Proofpoint-GUID: hSHyU4QiIDaugat5GsmgakY7jqrTZvTg X-Authority-Analysis: v=2.4 cv=A6r5rKWG c=1 sm=1 tr=0 ts=6ab0f5a1 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=DFGctsAPzAe98lL7n_0A:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 suspectscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 bulkscore=0 spamscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609210131 On 9/16/2026 11:34 AM, Qiang Yu wrote: > The controller now calls phy_init() from > qcom_pcie_host_init()/qcom_pcie_enable_resources() and phy_reset() > from inside its own core reset assert/deassert, so the PHY's reset > toggles alongside the controller's core reset as HPG requires. > Making that actually happen here needs phy_ops::init and > phy_ops::reset implemented, and phy_ops::power_on adjusted to match. > Split the combined phy_ops::power_on/power_off into > phy_ops::init/exit/reset/power_on to do that. > > phy_ops::init enables regulators and all clocks (pipe clock first) > and determines skip_init/skip_reset. phy_ops::reset toggles the > reset that skip_init picked. Register-table programming used to run > while the no-CSR reset was still asserted; now it runs afterwards, > in phy_ops::power_on. > > Adds skip_reset to struct qmp_pcie so phy_ops::reset and > phy_ops::power_on share the value phy_ops::init determined instead > of re-reading PCS registers. > > Signed-off-by: Qiang Yu > --- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 184 ++++++++++++++----------------- > 1 file changed, 80 insertions(+), 104 deletions(-) Verified the PCIe enumeration in IPQ9574 and IPQ5424 and it works fine. So, Tested-by: Kathiravan Thirumoorthy #IPQ9574-RDP433, IPQ5424-RDP466