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X-CSE-ConnectionGUID: pAUSJRGqT5qf4ZCNXCsFwQ== X-CSE-MsgGUID: Ov3JY70jRSCtFoS9i4uK7w== X-IronPort-AV: E=McAfee;i="6700,10204,11418"; a="64983260" X-IronPort-AV: E=Sophos;i="6.15,249,1739865600"; d="scan'208";a="64983260" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2025 08:18:05 -0700 X-CSE-ConnectionGUID: js3vkXVfS8+l3LLV9MNaUQ== X-CSE-MsgGUID: pW26e30nQzOP1v0/eOzgaQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,249,1739865600"; d="scan'208";a="138659653" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.205]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Apr 2025 08:18:01 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Tue, 29 Apr 2025 18:17:57 +0300 (EEST) To: Hans Zhang <18255117159@163.com> cc: lpieralisi@kernel.org, bhelgaas@google.com, manivannan.sadhasivam@linaro.org, kw@linux.com, cassel@kernel.org, robh@kernel.org, jingoohan1@gmail.com, thomas.richard@bootlin.com, linux-pci@vger.kernel.org, LKML Subject: Re: [PATCH v10 2/6] PCI: Clean up __pci_find_next_cap_ttl() readability In-Reply-To: <20250429125036.88060-3-18255117159@163.com> Message-ID: <66cdb108-80f5-fe7c-329b-8c60caf55b64@linux.intel.com> References: <20250429125036.88060-1-18255117159@163.com> <20250429125036.88060-3-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Tue, 29 Apr 2025, Hans Zhang wrote: > Refactor the __pci_find_next_cap_ttl() to improve code clarity: > - Replace magic number 0x40 with PCI_STD_HEADER_SIZEOF. > - Use ALIGN_DOWN() for position alignment instead of manual bitmask. > - Extract PCI capability fields via FIELD_GET() with standardized masks. > - Add necessary headers (linux/align.h, uapi/linux/pci_regs.h). > > The changes are purely non-functional cleanups, ensuring behavior remains > identical to the original implementation. > > Signed-off-by: Hans Zhang <18255117159@163.com> > --- > Changes since v9: > - None > > Changes since v8: > - Split into patch 1/6, patch 2/6. > - The > drivers/pci/pci.c | 10 ++++++---- > include/uapi/linux/pci_regs.h | 2 ++ > 2 files changed, 8 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 4d7c9f64ea24..1c29e8f20cb5 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -9,6 +9,7 @@ > */ > > #include > +#include > #include > #include > #include > @@ -30,6 +31,7 @@ > #include > #include > #include > +#include linux/pci.h will pull this in through so you don't need to add it (basically anywhere). > #include "pci.h" > > DEFINE_MUTEX(pci_slot_mutex); > @@ -432,17 +434,17 @@ static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, > pci_bus_read_config_byte(bus, devfn, pos, &pos); > > while ((*ttl)--) { > - if (pos < 0x40) > + if (pos < PCI_STD_HEADER_SIZEOF) > break; > - pos &= ~3; > + pos = ALIGN_DOWN(pos, 4); > pci_bus_read_config_word(bus, devfn, pos, &ent); > > - id = ent & 0xff; > + id = FIELD_GET(PCI_CAP_ID_MASK, ent); > if (id == 0xff) > break; > if (id == cap) > return pos; > - pos = (ent >> 8); > + pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, ent); > } > return 0; > } > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index ba326710f9c8..b59179e1210a 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -206,6 +206,8 @@ > /* 0x48-0x7f reserved */ > > /* Capability lists */ > +#define PCI_CAP_ID_MASK 0x00ff > +#define PCI_CAP_LIST_NEXT_MASK 0xff00 Consider adding a comment after the value as is done for most defines in this file. > > #define PCI_CAP_LIST_ID 0 /* Capability ID */ > #define PCI_CAP_ID_PM 0x01 /* Power Management */ > -- i.