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Tue, 14 Jan 2025 23:26:37 +0000 Date: Tue, 14 Jan 2025 17:26:31 -0600 From: Ira Weiny To: Terry Bowman , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v5 16/16] PCI/AER: Enable internal errors for CXL Upstream and Downstream Switch Ports Message-ID: <6786f2a7b2b7f_186d9b294f7@iweiny-mobl.notmuch> References: <20250107143852.3692571-1-terry.bowman@amd.com> <20250107143852.3692571-17-terry.bowman@amd.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250107143852.3692571-17-terry.bowman@amd.com> X-ClientProxiedBy: MW3PR05CA0026.namprd05.prod.outlook.com (2603:10b6:303:2b::31) To SA1PR11MB6733.namprd11.prod.outlook.com (2603:10b6:806:25c::17) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA1PR11MB6733:EE_|IA0PR11MB7883:EE_ X-MS-Office365-Filtering-Correlation-Id: 7705f578-74de-42f4-26e2-08dd34f2e446 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7416014|7053199007|921020; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?XFuS/0GUHenVTHgzUbf0S5w/T8traSE+xtE8THfLziUvrwNG7Jwsp2mHyDGW?= =?us-ascii?Q?TDy/YQtAxrIf1snTB/iNWZUCiFYHy4FwWPPoTUiMbdalKOZ/C7tyVqWHP2Yv?= =?us-ascii?Q?7jVeLUofi0xOVQJKvauUsaEZ7VY0uhmHf7BRb/LC3huNppy0+/8QdJVULRIC?= =?us-ascii?Q?zgdX/ujyjh9hhPr/kOEzwBCz9BSHA60s68XNNA59CdimySykblMubFF7wIXM?= =?us-ascii?Q?OZSDm41Eo58Wu54njEqHhPASRXOzsI4oIS9Xy3NC42Mz3oN6V1CKXLO+AznL?= =?us-ascii?Q?sdR3tqRur2Qoo1dbxOKXrKZ1Vt8jMKAQYVKeV0OMgkr3NTLoovbFVfQzPiq+?= =?us-ascii?Q?OuEgVDYWUxIW6mkt5BshISrmOr0Pj11IQESaX/S2dyTu9LG7jw8GlU3iXnaj?= =?us-ascii?Q?AV800mFh3Vp/8QLIak9b1YD4f31tJZ+Xbrh/TvCIY/DIr7RqW1/7I2fxRuBZ?= =?us-ascii?Q?KC3I7yQPJwgPfeF46fLUK8y3Kv2dGTE4aKj0CFmbS0juAHv9WOk5oJG352Qr?= =?us-ascii?Q?QNR3XSgkaFta1tTWVrzW4wKuVeQ2KXNNwnLXrckODbSUOJWCUBFttNDwk8uO?= =?us-ascii?Q?HuoPRj6SIQUdVLtKxKLkrud75njjSt4qxa569Z6u/Q2zMhOG8pnzXrS8HOGo?= =?us-ascii?Q?onYywse8SEK3rjSm8rbHiDRZOPaYrMsvhEB4Zcou0B/tmrB7oHWLyW3THjEp?= =?us-ascii?Q?EL8QIlulyjFhBaF/+Z6JZkat9StaZ/+gShZQou7HXMO+phfWGu2RHei0RMhm?= =?us-ascii?Q?VuKxMF8BkWOgYPshsm7NBtAU7tSt3RKAw0pU4vGtlxjdZbtUaoj9WvMMcT8/?= =?us-ascii?Q?L40XYqPW/9vxt9CBC28qOul9jtZJ9Na5216aVJFxAoEdIK1E+elJ14cfWtGP?= =?us-ascii?Q?pSM6+fk9gPBHnkFyxnwmGlLhIPdF5M+blZhwW9XBW6L8VbSKZtZ7bnFPxDC4?= =?us-ascii?Q?qrVMOquqEO6DBB5igm+puEJDTNCBFq4yBw6azQXnBvAaeLzIy1w+1uUsqfRJ?= =?us-ascii?Q?qIEmJe79sp0jZK12vctvYY4MACTsfch3QjR2WsoUhGDfH6LL67S93TsoAADL?= =?us-ascii?Q?CmkUXqV4HKvBQP8l/1CUzcyoEGSKM10cam9CZ0tKCCSakE0u2cj36KkLDPQi?= =?us-ascii?Q?j+8Dy0ygYHX/IxsAs1a3y+/87vtJSUuAIy7PPfCnvzcllSADdzMSG28ToNs7?= =?us-ascii?Q?VxXN/n8jYbcJPo0LheGig/EijUrRafIQrns0Dht3V7h5VPs4zDDveCwDu7ch?= =?us-ascii?Q?5vinU0uNcL/zQUJPK5H80288x337xVYwZj8GfDgslRssi/6jAt3Mkh0Z1htb?= =?us-ascii?Q?bjvErxiKDhGYT1LEa9VrzegNrBWLqBeTXmU35wmni543L/Li8/l1qKSGuEkp?= =?us-ascii?Q?gU9S6cytJY1plzsH/a2PKmR5rfYInJbCqeYBooiIPltmPvF36C46W92Wl7K/?= =?us-ascii?Q?cMzc5bX4UQ+oOX0VVJspPfMfD6/i5bxWOBOV1vXL8Xl2pzfvM7leg0Sfn87v?= =?us-ascii?Q?Jp5BcO5RsoqS6SQCCFyW8gWAQhyBEagU2KRjvmTk+xPc0oX9ErxL8IXNdYhR?= =?us-ascii?Q?T2z3pgWPhHib6PAX/g2dAc1zmSwdiQdEYW1HVxRM?= X-MS-Exchange-CrossTenant-Network-Message-Id: 7705f578-74de-42f4-26e2-08dd34f2e446 X-MS-Exchange-CrossTenant-AuthSource: SA1PR11MB6733.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jan 2025 23:26:37.5317 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: g2PJPm1aAaKSWxc8xMQ/HI2RH1bZDm/K4TH2d7nfXrtYNBGpL9z1p5oF/VSWlooZXGQXRGPoUtFHFsvvp+rYjw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR11MB7883 X-OriginatorOrg: intel.com Terry Bowman wrote: > The AER service driver enables PCIe Uncorrectable Internal Errors (UIE) and > Correctable Internal errors (CIE) for CXL Root Ports. The UIE and CIE are > used in reporting CXL Protocol Errors. The same UIE/CIE enablement is > needed for CXL Upstream Switch Ports and CXL Downstream Switch Ports > inorder to notify the associated Root Port and OS.[1] > > Export the AER service driver's pci_aer_unmask_internal_errors() function > to CXL namespace. > > Remove the function's dependency on the CONFIG_PCIEAER_CXL kernel config > because it is now an exported function. This seems wrong to me. As of this patch CXL_PCI requires PCIEAER_CXL for the AER code to handle the errors which were just enabled. To keep PCIEAER_CXL optional pci_aer_unmask_internal_errors() should be stubbed out in aer.h if !CONFIG_PCIEAER_CXL. Ira > > Call pci_aer_unmask_internal_errors() during RAS initialization in: > cxl_uport_init_ras_reporting() and cxl_dport_init_ras_reporting(). > > [1] PCIe Base Spec r6.2-1.0, 6.2.3.2.2 Masking Individual Errors > > Signed-off-by: Terry Bowman > Reviewed-by: Jonathan Cameron > --- > drivers/cxl/core/pci.c | 2 ++ > drivers/pci/pcie/aer.c | 5 +++-- > include/linux/aer.h | 1 + > 3 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 9c162120f0fe..c62329cd9a87 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -895,6 +895,7 @@ void cxl_uport_init_ras_reporting(struct cxl_port *port) > > cxl_assign_port_error_handlers(pdev); > devm_add_action_or_reset(&port->dev, cxl_clear_port_error_handlers, pdev); > + pci_aer_unmask_internal_errors(pdev); > } > EXPORT_SYMBOL_NS_GPL(cxl_uport_init_ras_reporting, "CXL"); > > @@ -935,6 +936,7 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport) > } > cxl_assign_port_error_handlers(pdev); > devm_add_action_or_reset(&port->dev, cxl_clear_port_error_handlers, pdev); > + pci_aer_unmask_internal_errors(pdev); > put_device(&port->dev); > } > EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index 68e957459008..e6aaa3bd84f0 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -950,7 +950,6 @@ static bool is_internal_error(struct aer_err_info *info) > return info->status & PCI_ERR_UNC_INTN; > } > > -#ifdef CONFIG_PCIEAER_CXL > /** > * pci_aer_unmask_internal_errors - unmask internal errors > * @dev: pointer to the pcie_dev data structure > @@ -961,7 +960,7 @@ static bool is_internal_error(struct aer_err_info *info) > * Note: AER must be enabled and supported by the device which must be > * checked in advance, e.g. with pcie_aer_is_native(). > */ > -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) > +void pci_aer_unmask_internal_errors(struct pci_dev *dev) > { > int aer = dev->aer_cap; > u32 mask; > @@ -974,7 +973,9 @@ static void pci_aer_unmask_internal_errors(struct pci_dev *dev) > mask &= ~PCI_ERR_COR_INTERNAL; > pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); > } > +EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL"); > > +#ifdef CONFIG_PCIEAER_CXL > static bool is_cxl_mem_dev(struct pci_dev *dev) > { > /* > diff --git a/include/linux/aer.h b/include/linux/aer.h > index 4b97f38f3fcf..093293f9f12b 100644 > --- a/include/linux/aer.h > +++ b/include/linux/aer.h > @@ -55,5 +55,6 @@ void pci_print_aer(struct pci_dev *dev, int aer_severity, > int cper_severity_to_aer(int cper_severity); > void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, > int severity, struct aer_capability_regs *aer_regs); > +void pci_aer_unmask_internal_errors(struct pci_dev *dev); > #endif //_AER_H_ > > -- > 2.34.1 >