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Wed, 26 Feb 2025 02:00:02 +0000 Date: Tue, 25 Feb 2025 18:00:00 -0800 From: Dan Williams To: Jonathan Cameron , Dan Williams CC: , Bjorn Helgaas , "Lukas Wunner" , Samuel Ortiz , "Alexey Kardashevskiy" , Xu Yilun , , Subject: Re: [PATCH 06/11] samples/devsec: PCI device-security bus / endpoint sample Message-ID: <67be75a01ef00_1a772944c@dwillia2-xfh.jf.intel.com.notmuch> References: <173343739517.1074769.13134786548545925484.stgit@dwillia2-xfh.jf.intel.com> <173343743095.1074769.17985181033044298157.stgit@dwillia2-xfh.jf.intel.com> <20250130132129.000027ad@huawei.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250130132129.000027ad@huawei.com> X-ClientProxiedBy: MW4PR03CA0258.namprd03.prod.outlook.com (2603:10b6:303:b4::23) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|MW5PR11MB5764:EE_ X-MS-Office365-Filtering-Correlation-Id: 71cd097a-ed6e-441c-b8d9-08dd56094863 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?z8+M7vLwOlADqC9hUp4JQmVJEAHnXsPYzJ3yJ6z9nQlzRBzU/+9BaRZps4ZT?= =?us-ascii?Q?yF7Tcd7an0iX+VL4APg7THjunAxUpJYLxLb8F28w0ETJ4j7R+oA1/DhE3KLb?= =?us-ascii?Q?9PzA21XXw3VEBhwcKj8Ki8PCKikuwROVU/etWLYqplNK1Gy5ucHZHjV/7idt?= =?us-ascii?Q?ykdek5sm+kkM+ba4b+0y9G5f3uACsKbyCWjJUiAMayzwFm0kF8mOplUgSdRG?= =?us-ascii?Q?Th6Xt74myIQaJJ7DjiEHlCO3Xpr4c56inO3r55bZhWVGsyhMEhPLEzu35jNs?= =?us-ascii?Q?tINQ+iyyveP53YvbKMAojCb8p9AjWpR1oJibmWe/cncFNh0H6eWobaSjsiJe?= =?us-ascii?Q?7ZE/QB9yKECYGHd9qPJrTmkhetO8jo2KoUTpgcjdTpKKAUgA3AwFQeCN66ez?= =?us-ascii?Q?o93IZUZs+hRwuNlQcoWLRDQf8OQ1ZJPH0NfhC3dzs8Hq82Q/O8/6714al5eP?= =?us-ascii?Q?4RYetkr7hiRVMZexWBen5uoSVktRUju9U01DIOOSg7DaVibSNCMM52nkkoOy?= =?us-ascii?Q?nPFkm7CofZ3bDaYQATcI7RClL+HIYTu39cBMlntKHEOdmONXBb+RZHsymCOL?= =?us-ascii?Q?wSKMEuNhTqzNH6zGHzWqvcdpOGBc8jtbWTOUI+nO+EzAXq7wip19yLpp3cXH?= =?us-ascii?Q?CFF1FVxYs4QOoYOuPsUSLfbEYZs6/ChWfHzQL0fWsMPSEy7ZOXRpH8kTwkoa?= =?us-ascii?Q?2VKSmbK/b+iYM0cQh1TG3pAyplSmjjYD/SfkSYh36n0A92QWFbTkH17+42GU?= =?us-ascii?Q?U0nu7Wx7MenwoQSL+BnnOsdTWS0AzCNzb1Yl33MTVw5fRR3Np4fdr5m7o25V?= =?us-ascii?Q?pqCs/AYn3kLmaHkb+ZU5eNjGF8kBA3Oxrmf5bATS7lsAHe5sQ9X0lkFnFbYy?= =?us-ascii?Q?n9uv6NkzWg3UJuJC8XLY8V3Hrrql2Lrk0m1TisWlI3mmI1Xs7sMM6lnmyMKl?= =?us-ascii?Q?ucK8G9gAQ+Av8J7w5Gkuwtx6yWxxpKuALxM1Xq+GcOvXijWvLG/99Iv4i9cc?= =?us-ascii?Q?zuYhGFxhEOT1+8i3xbELcqisX6GyYGwd/Pr/lyc9OhJe/+22dtdBDB58+nfU?= =?us-ascii?Q?TUXOOaOlfbjmU25vIhBRlJmPcS3rDAALblRwa0y9P0A4BolWKlCdzEjncon7?= =?us-ascii?Q?ifLos8nMJfGo5AxDMGqI2kVWwdqkJAl+oH05htKUKaYGTidIj0LNMeWa5APS?= =?us-ascii?Q?YXuy8vfLfzAYrmu6ANY4Hmn8sGyMTG2zBX/TeaQxKAkFrsjR2mnGCLUYtVkS?= =?us-ascii?Q?AT+gl/0mfbt4YYDBBlOms+g38ss6uhq1b2wwHHvGddqMo0eg7PhStJwZOSl5?= =?us-ascii?Q?DpRWQiN1zPtSTfK0ZO30ZyML/ZkTgbwApnZRQTtns53L1+aGuLidV8Hrjxvl?= =?us-ascii?Q?XUBoBGsYOS9W/2XIC2GAuMHvhdLo9bIcksWKvARebjymBcZ5xh7hTbHPNQdQ?= =?us-ascii?Q?Jk8XVA5ce0Vxb6c/Z+pNdv16LuplArBQF/047UnbP9jUDJxEt3tbog3avsAF?= =?us-ascii?Q?gkTZ52N2saUmAsVb00FB9SJlrcCUruBzdfMzXbmQnKqBOHE1EVsBe3UCJsDj?= =?us-ascii?Q?Nze5+kUJppHoS/L4nnKdeBxHzq54WLGD3ZBUd4gl7ctuS8PiPpcHiybroWRD?= =?us-ascii?Q?8A=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 71cd097a-ed6e-441c-b8d9-08dd56094863 X-MS-Exchange-CrossTenant-AuthSource: PH8PR11MB8107.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Feb 2025 02:00:02.6975 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iTBJyN7We2U3I3adSgY9H40609gXqvSOUwWlDUg3K4hVbRmH2FCuOudYYZoY0QssXYMVucWJ1Fdl44BrIIEuPwSHXhtftn92wupjqAQyUIM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR11MB5764 X-OriginatorOrg: intel.com Jonathan Cameron wrote: > On Thu, 05 Dec 2024 14:23:51 -0800 > Dan Williams wrote: > > > Establish just enough emulated PCI infrastructure to register a sample > > TSM (platform security manager) driver and have it discover an IDE + TEE > > (link encryption + device-interface security protocol (TDISP)) capable > > device. > > > > Use the existing a CONFIG_PCI_BRIDGE_EMUL to emulate an IDE capable root > > port, and open code the emulation of an endpoint device via simulated > > configuration cycle responses. > > > > The devsec_tsm driver responds to the PCI core TSM operations as if it > > successfully exercised the given interface security protocol message. > > > > The devsec_bus and devsec_tsm drivers can be loaded in either order to > > reflect cases like SEV-TIO where the TSM is PCI-device firmware, and > > cases like TDX Connect where the TSM is a software agent running on the > > host CPU. > > > > Follow-on patches add common code for TSM managed IDE establishment. For > > now, just successfully complete setup and teardown of the DSM (device > > security manager) context as a building block for management of TDI > > (trusted device interface) instances. > > > > # modprobe devsec_bus > > devsec_bus devsec_bus: PCI host bridge to bus 10000:00 > > pci_bus 10000:00: root bus resource [bus 00-01] > > pci_bus 10000:00: root bus resource [mem 0xf000000000-0xffffffffff 64bit] > > pci 10000:00:00.0: [8086:7075] type 01 class 0x060400 PCIe Root Port > > pci 10000:00:00.0: PCI bridge to [bus 00] > > pci 10000:00:00.0: bridge window [io 0x0000-0x0fff] > > pci 10000:00:00.0: bridge window [mem 0x00000000-0x000fffff] > > pci 10000:00:00.0: bridge window [mem 0x00000000-0x000fffff 64bit pref] > > pci 10000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring > > pci 10000:01:00.0: [8086:ffff] type 00 class 0x000000 PCIe Endpoint > > pci 10000:01:00.0: BAR 0 [mem 0xf000000000-0xf0001fffff 64bit pref] > > pci_doe_abort: pci 10000:01:00.0: DOE: [100] Issuing Abort > > pci_doe_cache_protocols: pci 10000:01:00.0: DOE: [100] Found protocol 0 vid: 1 prot: 1 > > pci 10000:01:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force' > > pci 10000:00:00.0: PCI bridge to [bus 01] > > pci_bus 10000:01: busn_res: [bus 01] end is updated to 01 > > # modprobe devsec_tsm > > devsec_tsm_pci_probe: pci 10000:01:00.0: devsec: tsm enabled > > __pci_tsm_init: pci 10000:01:00.0: TSM: Device security capabilities detected ( ide tee ), TSM attach > > > > Cc: Bjorn Helgaas > > Cc: Lukas Wunner > > Cc: Samuel Ortiz > > Cc: Alexey Kardashevskiy > > Cc: Xu Yilun > > Signed-off-by: Dan Williams > Hi Dan, > > A few minor comments as I was reading this. Mostly just trying > to get my head around it hence they are all fairly superficial things. > > Jonathan > > > diff --git a/samples/devsec/bus.c b/samples/devsec/bus.c > > new file mode 100644 > > index 000000000000..47dbe4e1b648 > > --- /dev/null > > +++ b/samples/devsec/bus.c > > > > +static void destroy_iomem_pool(void *data) > > There is a devm_gen_pool_create you can probably use. Indeed there is, thanks. [..] > Similar to the case below. I'd rather see a per dev devm_ cleanup > than relying on unified cleanup and that array having null entrees. > Should end up easier to follow. Might require devsec dev to have > a reference back to the pool though. Done for ports and devs. The arrays are used during PCI bus operations. This made me realize that I should be putting the device and port allocation *before* the PCI bus creation to make sure those arrays are dead and idle before the they are invalidated by the port and dev devres actions. [..] > > +static int init_port(struct devsec_port *devsec_port) > > +{ > > + struct pci_bridge_emul *bridge = &devsec_port->bridge; > > + int rc; > > + > > + bridge->conf.vendor = cpu_to_le16(0x8086); > > + bridge->conf.device = cpu_to_le16(0x7075); > > + bridge->subsystem_vendor_id = cpu_to_le16(0x8086); > > + bridge->conf.class_revision = cpu_to_le32(0x1); > > + > > + bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); > > + bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); > > + > > + bridge->has_pcie = true; > > + bridge->pcie_conf.devcap = cpu_to_le16(PCI_EXP_DEVCAP_FLR); > > + bridge->pcie_conf.lnksta = cpu_to_le16(PCI_EXP_LNKSTA_CLS_2_5GB); > > + > > + bridge->data = devsec_port; > > + bridge->ops = &devsec_bridge_ops; > Maybe > *bridge = (struct pci_bridge_emul) { > }; > appropriate here. Sure. > > + > > + init_ide(&devsec_port->ide); > > + > > + rc = pci_bridge_emul_init(bridge, 0); > > return pci_bridge_emul_init() unless a later patch is going to add more here. Ok.