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X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2025 18:34:05.2027 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec880010-7064-425a-d80f-08de26d10db4 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D12.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1PR10MB7571 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTE4MDE0OSBTYWx0ZWRfX/cSIXhwpS49S H58R9LBWczNAuMPf7EURTIFYRg+jrCQk+4znGP2nTlTmrBTRfkwAGQJvwxDFREQu64V6ppdGoLf 17s7hethE6xUhUOax1j8iArXxxgxCOK0abUOx/E8BZEGfno0fyGzeL2Az4dh1v/auLFJuh3s0Xy 2M58KRqz649fmlJqaiexNwLNv7ivN2SkdBk8PP1MWMTxgguoarKLxE/XPiMXcuoKGRnJ8GpjTNO f76rw8CPvyaBqOE8jK/r6L5tXnFrcxj/8c4Vtany7IqAHBzOwOlWYj1OKCu8IV9DKUHYAefOFnB GaTRa/r25t/qCJhFxRzrYJOJx8qEzMEKGcsQSFC2ORsGLN+JPRlUYEAOFohZdaXnf3U75lly0mO /R4PhFVgwvbs85yE/OriCQhMxdyvYw== X-Authority-Analysis: v=2.4 cv=SaL6t/Ru c=1 sm=1 tr=0 ts=691cbc23 cx=c_pps a=4X+iVNKrLEFvYFcl14eRNw==:117 a=d6reE3nDawwanmLcZTMRXA==:17 a=6eWqkTHjU83fiwn7nKZWdM+Sl24=:19 a=RA8ZoFPxCIQA:10 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s63m1ICgrNkA:10 a=KrXZwBdWH7kA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=8b9GpE9nAAAA:8 a=KlQPxW_TAIvn8hAYAncA:9 a=QEXdDO2ut3YA:10 a=X8_hmcNjPp8A:10 a=VmwSssl72cIA:10 a=T3LWEMljR5ZiDmsYVIUa:22 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-GUID: o4gfqP86EB7qQp-5ecozdyxwVyLTJFro X-Proofpoint-ORIG-GUID: o4gfqP86EB7qQp-5ecozdyxwVyLTJFro X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-18_02,2025-11-18_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 adultscore=0 malwarescore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511180149 On 11/17/25 21:00, Bjorn Helgaas wrote: > On Mon, Nov 17, 2025 at 01:04:47PM +0100, Christian Bruel wrote: >> On 11/14/25 19:59, Bjorn Helgaas wrote: >>> On Fri, Nov 14, 2025 at 08:45:52AM +0100, Christian Bruel wrote: >>>> If the host has deasserted PERST# and started link training before the link >>>> is started on EP side, enabling LTSSM before the endpoint registers are >>>> initialized in the perst_irq handler results in probing incorrect values. >>>> >>>> Thus, wait for the PERST# level-triggered interrupt to start link training >>>> at the end of initialization and cleanup the stm32_pcie_[start stop]_link >>>> functions. >>> >>> I've seen this kind of thing in other drivers, and I wondered whether >>> it was safe because the host asserts and deasserts PERST# >>> asynchronously, independent of anything the endpoint is doing. >>> >>> I assume it's possible that the host deasserts PERST# before this >>> driver has the stm32_pcie_ep_perst_irq_thread() thread set up. If >>> that happens and the driver doesn't see the PERST# interrupt, does >>> everything still work correctly? >> >> yes it does. the PERST# interrupt is level-triggered and, if already >> de-asserted, fires only when enabled (it is NOAUTOEN) with start_link. >> >> At that point, the host can enumerate by performing a manual rescan or >> rebind the PCIe driver, restarting the entire probe sequence. >> >> Tested the pcie_epf_test driver with various power-up sequences: full >> power-up the host or device first, and stop or standby PM suspend/resume. > > Help me think through this. I guess the interesting case is when the > host boots first and enumerates devices before the stm32 endpoint is > ready, right? > > I suppose the endpoint LTSSM is initially disabled, so the link is > down, and the host enumeration didn't find anything? yes. When the device is not started (start_link) dw_pcie_wait_for_link() fails and pci_host_probe() only register the root port: /* * Note: Skip the link up delay only when a Link Up IRQ is present. * If there is no Link Up IRQ, we should not bypass the delay * because that would require users to manually rescan for devices. */ if (!pp->use_linkup_irq) /* Ignore errors, the link may come up later */ dw_pcie_wait_for_link(pci); ret = pci_host_probe(bridge); > > Where does the link come up? I see the pci_epc_start_store() that > eventually leads to stm32_pcie_start_link(), which enables perst_irq. The link appears when explicitly requested by writing '1' into the bound endpoint device driver sysfs 'start' once the device is configured. see https://www.kernel.org/doc/html/latest/PCI/endpoint/pci-test-howto.html But how pci_epc_start_store() is iterated from the configfs_write_iter() mechanism is beyond my knowledge... > Since you requested perst_irq with IRQF_TRIGGER_HIGH, and PERST# is > deasserted, does that trigger stm32_pcie_ep_perst_irq_thread() and > call stm32_pcie_perst_deassert() to enable the LTSSM? perst_gpio is active low. So requesting the perst_irq with IRQF_TRIGGER_HIGH triggers when deasserted. This parts is quite confusing (for me) because gpiod_get_value() correctly returns 0 when the gpio is de-asserted, when the irq API does not know about active low so we must use TRIGGER_HIGH > > When the link comes up, if the Downstream Port supports hotplug and > pciehp is enabled, it might notice the link-up event and treat this as > a hot-add? yes, I just tried with a host pc with hot-plug enabled. lspci found the stm32 EP, as you anticipated > > Otherwise the user would have to manually rescan to notice the > endpoint? indeed, this is how I proceed when the host does not support hot-plug, thank you, Christian > >>>> Signed-off-by: Christian Bruel >>>> --- >>>> drivers/pci/controller/dwc/pcie-stm32-ep.c | 38 ++++++------------------------ >>>> 1 file changed, 7 insertions(+), 31 deletions(-) >>>> >>>> diff --git a/drivers/pci/controller/dwc/pcie-stm32-ep.c b/drivers/pci/controller/dwc/pcie-stm32-ep.c >>>> index 3400c7cd2d88a279c49ef36a99fc7537c381c384..d0654bb43759bb8d0f0d7badbf7bdae839241fcf 100644 >>>> --- a/drivers/pci/controller/dwc/pcie-stm32-ep.c >>>> +++ b/drivers/pci/controller/dwc/pcie-stm32-ep.c >>>> @@ -37,36 +37,9 @@ static void stm32_pcie_ep_init(struct dw_pcie_ep *ep) >>>> dw_pcie_ep_reset_bar(pci, bar); >>>> } >>>> -static int stm32_pcie_enable_link(struct dw_pcie *pci) >>>> -{ >>>> - struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); >>>> - >>>> - regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, >>>> - STM32MP25_PCIECR_LTSSM_EN, >>>> - STM32MP25_PCIECR_LTSSM_EN); >>>> - >>>> - return dw_pcie_wait_for_link(pci); >>>> -} >>>> - >>>> -static void stm32_pcie_disable_link(struct dw_pcie *pci) >>>> -{ >>>> - struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); >>>> - >>>> - regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, STM32MP25_PCIECR_LTSSM_EN, 0); >>>> -} >>>> - >>>> static int stm32_pcie_start_link(struct dw_pcie *pci) >>>> { >>>> struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); >>>> - int ret; >>>> - >>>> - dev_dbg(pci->dev, "Enable link\n"); >>>> - >>>> - ret = stm32_pcie_enable_link(pci); >>>> - if (ret) { >>>> - dev_err(pci->dev, "PCIe cannot establish link: %d\n", ret); >>>> - return ret; >>>> - } >>>> enable_irq(stm32_pcie->perst_irq); >>>> @@ -77,11 +50,7 @@ static void stm32_pcie_stop_link(struct dw_pcie *pci) >>>> { >>>> struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci); >>>> - dev_dbg(pci->dev, "Disable link\n"); >>>> - >>>> disable_irq(stm32_pcie->perst_irq); >>>> - >>>> - stm32_pcie_disable_link(pci); >>>> } >>>> static int stm32_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, >>>> @@ -152,6 +121,8 @@ static void stm32_pcie_perst_assert(struct dw_pcie *pci) >>>> dev_dbg(dev, "PERST asserted by host\n"); >>>> + regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, STM32MP25_PCIECR_LTSSM_EN, 0); >>>> + >>>> pci_epc_deinit_notify(ep->epc); >>>> stm32_pcie_disable_resources(stm32_pcie); >>>> @@ -192,6 +163,11 @@ static void stm32_pcie_perst_deassert(struct dw_pcie *pci) >>>> pci_epc_init_notify(ep->epc); >>>> + /* Enable link training */ >>>> + regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, >>>> + STM32MP25_PCIECR_LTSSM_EN, >>>> + STM32MP25_PCIECR_LTSSM_EN); >>>> + >>>> return; >>>> err_disable_resources: >>>> >>>> --- >>>> base-commit: 31115ecec74fe5c679a149d7037009f26b3aa8a9 >>>> change-id: 20251113-perst_ep-0b57b9679cf9 >>>> >>>> Best regards, >>>> -- >>>> Christian Bruel >>>> >>