Re: [PATCH v4 06/10] PCI: Add PCIe Device 3 Extended Capability enumeration

[<dan.j.williams@intel.com>]

Bjorn Helgaas wrote:
> On Thu, Jul 17, 2025 at 11:33:54AM -0700, Dan Williams wrote:
> > PCIe 6.2 Section 7.7.9 Device 3 Extended Capability Structure,
> > enumerates new link capabilities and status added for Gen 6 devices. One
> 
> s/ added for Gen 6 devices//
> 
> I know the "Gen 6 device" terminology is pervasive, but the spec
> suggests avoiding it because it's so ambiguous.

Ok.

> 
> > of the link details enumerated in that register block is the "Segment
> > Captured" status in the Device Status 3 register. That status is
> > relevant for enabling IDE (Integrity & Data Encryption) whereby
> > Selective IDE streams can be limited to a given Requester ID range
> > within a given segment.
> > 
> > If a device has captured its Segment value then it knows that PCIe Flit
> > Mode is enabled via all links in the path that a configuration write
> > traversed. IDE establishment requires that "Segment Base" in
> > IDE RID Association Register 2 (PCIe 6.2 Section 7.9.26.5.4.2) be
> > programmed if the RID association mechanism is in effect.
> > 
> > When / if IDE + Flit Mode capable devices arrive, the PCI core needs to
> > setup the segment base when using the RID association facility, but no
> > known deployments today depend on this.
> 
> So far this mentions a lot of facts, but only the subject hints at
> what it does.  I guess it just captures the Flit Mode status, inferred
> by Segment Captured?
> 
> I'm OK with basically just saying *that*, and moving some of the
> implications to places where we depend on them.

Agree, too wordy. Trimmed to:

PCIe r7.0 Section 7.7.9 Device 3 Extended Capability Structure, defines the
canonical location for determining the Flit Mode of a device. This status
is a dependency for PCIe IDE enabling. Add a new fm_enabled flag to 'struct
pci_dev'.