From: <dan.j.williams@intel.com>
To: Aneesh Kumar K.V <aneesh.kumar@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
<linux-coco@lists.linux.dev>, <linux-pci@vger.kernel.org>
Cc: <gregkh@linuxfoundation.org>, <bhelgaas@google.com>,
<yilun.xu@linux.intel.com>, <aik@amd.com>
Subject: Re: [PATCH 5/7] PCI/TSM: Add Device Security (TVM Guest) operations support
Date: Tue, 9 Sep 2025 22:31:05 -0700 [thread overview]
Message-ID: <68c10d197df27_5addd100ec@dwillia2-mobl4.notmuch> (raw)
In-Reply-To: <yq5aplc61crg.fsf@kernel.org>
Aneesh Kumar K.V wrote:
> Dan Williams <dan.j.williams@intel.com> writes:
>
> > PCIe Trusted Execution Environment Device Interface Security Protocol
> > (TDISP) has two distinct sets of operations. The first, currently enabled
> > in driver/pci/tsm.c, enables the VMM to authenticate the physical function
> > (PCIe Component Measurement and Authentication (CMA)), establish a secure
> > message passing session (DMTF SPDM), and establish physical link security
> > (PCIe Integrity and Data Encryption (IDE)). The second set lets the TVM
> > manage the security state of assigned devices (TEE Device Interfaces
> > (TDIs)). Enable the latter with three new 'struct pci_tsm_ops' operations:
> >
> > - lock(): Transition the device to the TDISP state. In this mode
> > the device is responsible for validating that it is in a secure
> > configuration and will transition to the TDISP ERROR state if those
> > settings are modified. Device Security Manager (DSM) and the TEE
> > Security Manager (TSM) enforce that the device is not permitted to issue
> > T=1 traffic in this mode.
> >
[..]
> > @@ -453,6 +477,265 @@ static ssize_t disconnect_store(struct device *dev,
> > }
> > static DEVICE_ATTR_WO(disconnect);
> >
> > +static struct resource **alloc_encrypted_resources(struct pci_dev *pdev,
> > + struct resource **__res)
> > +{
> > + int i;
> > +
> > + memset(__res, 0, sizeof(struct resource *) * PCI_NUM_RESOURCES);
> > +
> > + for (i = 0; i < PCI_NUM_RESOURCES; i++) {
> > + unsigned long flags = pci_resource_flags(pdev, i);
> > + resource_size_t len = pci_resource_len(pdev, i);
> > +
> > + if (!len || !(flags & IORESOURCE_MEM))
> > + continue;
> > +
> > +
> > + __res[i] = kzalloc(sizeof(struct resource), GFP_KERNEL);
> > + if (!__res[i])
> > + break;
> > +
> > + *__res[i] = DEFINE_RES_NAMED_DESC(pci_resource_start(pdev, i),
> > + len, "PCI MMIO Encrypted",
> > + flags, IORES_DESC_ENCRYPTED);
> > +
> >
>
> Not all resources are secure/encrypted. For example, if secure
> interrupts are not supported, then the MSI-X table and PBA BARs remain
> shared resources between the guest and the hypervisor.
I failed to mention this in the changelog, but part of thinking here is
that the mixed security state of a device based on interface report I
was expecting to be follow-on work. I.e. that minimum viable base case
is all MMIO is private of a private PCI device.
However, we can still keep the PCI/TSM core implementation equally
simple by moving these iomem manipulation routines to library helpers
that a TSM driver can optionally call as part of ->accept().
> In ARM CCA, the interface report is used to determine the nature of each
> region. When ioremap() is called, it relies on the Realm IPA state of
> the guest physical address to decide whether the mapping should be
> treated as shared or private [1], [2].
>
> With this change we report the msix table and pba range as encrypted in
> /proc/iomem
>
> 50012000-50012fff : PCI MMIO Encrypted
> 50012000-50012fff : 0000:00:01.0
> 50012000-50012fff : ahci
> 50013000-50013fff : PCI MMIO Encrypted
> 50013000-50013fff : 0000:00:01.0
> 50013000-50013fff : ahci
Unless these interface reports from different archs are all coming back
in a common format that can be parsed I do think it is a good idea to
reflect private MMIO in /proc/iomem regardless of how the arch
communicates to ioremap() to apply the private mapping pgprot setting.
In the meantime I will move these to optional library calls.
next prev parent reply other threads:[~2025-09-10 5:31 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-27 3:52 [PATCH 0/7] PCI/TSM: TEE I/O infrastructure Dan Williams
2025-08-27 3:52 ` [PATCH 1/7] PCI/TSM: Add pci_tsm_{bind,unbind}() methods for instantiating TDIs Dan Williams
2025-09-02 0:12 ` Alexey Kardashevskiy
2025-09-02 15:04 ` Aneesh Kumar K.V
2025-09-10 4:47 ` dan.j.williams
2025-09-10 4:46 ` dan.j.williams
2025-09-02 15:05 ` Aneesh Kumar K.V
2025-09-10 4:50 ` dan.j.williams
2025-09-03 15:17 ` Aneesh Kumar K.V
2025-09-04 10:38 ` Alexey Kardashevskiy
2025-09-04 12:56 ` Aneesh Kumar K.V
2025-09-05 2:32 ` Alexey Kardashevskiy
2025-09-10 5:09 ` dan.j.williams
2025-08-27 3:52 ` [PATCH 2/7] PCI/TSM: Add pci_tsm_guest_req() for managing TDIs Dan Williams
2025-08-28 9:53 ` Alexey Kardashevskiy
2025-08-28 22:07 ` dan.j.williams
2025-08-29 2:21 ` Alexey Kardashevskiy
2025-08-30 2:37 ` dan.j.williams
2025-09-01 23:49 ` Alexey Kardashevskiy
2025-09-08 11:09 ` Alexey Kardashevskiy
2025-09-10 5:35 ` dan.j.williams
2025-10-10 4:48 ` Xu Yilun
2025-08-28 13:02 ` Aneesh Kumar K.V
2025-08-28 22:14 ` dan.j.williams
2025-08-27 3:52 ` [PATCH 3/7] device core: Introduce confidential device acceptance Dan Williams
2025-08-27 6:14 ` Greg KH
2025-08-28 20:07 ` dan.j.williams
2025-09-16 16:58 ` Jonathan Cameron
2025-08-27 3:52 ` [PATCH 4/7] x86/ioremap, resource: Introduce IORES_DESC_ENCRYPTED for encrypted PCI MMIO Dan Williams
2025-09-17 21:30 ` Jason Gunthorpe
2025-10-07 8:23 ` Alexey Kardashevskiy
2025-10-07 21:31 ` Alexey Kardashevskiy
2025-08-27 3:52 ` [PATCH 5/7] PCI/TSM: Add Device Security (TVM Guest) operations support Dan Williams
2025-09-03 15:22 ` Aneesh Kumar K.V
2025-09-10 5:15 ` dan.j.williams
2025-09-11 8:31 ` Aneesh Kumar K.V
2025-09-04 15:02 ` Aneesh Kumar K.V
2025-09-10 5:31 ` dan.j.williams [this message]
2025-09-16 17:10 ` Jonathan Cameron
2025-08-27 3:52 ` [PATCH 6/7] samples/devsec: Introduce a "Device Security TSM" sample driver Dan Williams
2025-08-27 12:39 ` Jason Gunthorpe
2025-08-27 23:47 ` Alexey Kardashevskiy
2025-08-28 21:38 ` dan.j.williams
2025-08-29 16:02 ` Jason Gunthorpe
2025-08-29 20:00 ` dan.j.williams
2025-08-29 23:34 ` Jason Gunthorpe
2025-08-27 3:52 ` [PATCH 7/7] tools/testing/devsec: Add a script to exercise samples/devsec/ Dan Williams
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=68c10d197df27_5addd100ec@dwillia2-mobl4.notmuch \
--to=dan.j.williams@intel.com \
--cc=aik@amd.com \
--cc=aneesh.kumar@kernel.org \
--cc=bhelgaas@google.com \
--cc=gregkh@linuxfoundation.org \
--cc=linux-coco@lists.linux.dev \
--cc=linux-pci@vger.kernel.org \
--cc=yilun.xu@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).