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From: <dan.j.williams@intel.com>
To: Jonathan Cameron <jonathan.cameron@huawei.com>,
	Dan Williams <dan.j.williams@intel.com>
Cc: <linux-coco@lists.linux.dev>, <linux-pci@vger.kernel.org>,
	<aik@amd.com>, <yilun.xu@linux.intel.com>,
	<aneesh.kumar@kernel.org>, <bhelgaas@google.com>,
	<gregkh@linuxfoundation.org>, Lukas Wunner <lukas@wunner.de>,
	Samuel Ortiz <sameo@rivosinc.com>
Subject: Re: [PATCH v7 8/9] PCI/IDE: Report available IDE streams
Date: Thu, 30 Oct 2025 13:48:39 -0700	[thread overview]
Message-ID: <6903cf271538a_10e91003e@dwillia2-mobl4.notmuch> (raw)
In-Reply-To: <20251029163109.000030ae@huawei.com>

Jonathan Cameron wrote:
> On Thu, 23 Oct 2025 19:04:17 -0700
> Dan Williams <dan.j.williams@intel.com> wrote:
> 
> > The limited number of link-encryption (IDE) streams that a given set of
> > host bridges supports is a platform specific detail. Provide
> > pci_ide_init_nr_streams() as a generic facility for either platform TSM
> > drivers, or PCI core native IDE, to report the number available streams.
> > After invoking pci_ide_init_nr_streams() an "available_secure_streams"
> > attribute appears in PCI host bridge sysfs to convey that count.
> > 
> > Introduce a device-type, @pci_host_bridge_type, now that both a release
> > method and sysfs attribute groups are being specified for all 'struct
> > pci_host_bridge' instances.
> > 
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Lukas Wunner <lukas@wunner.de>
> > Cc: Samuel Ortiz <sameo@rivosinc.com>
> > Cc: Alexey Kardashevskiy <aik@amd.com>
> > Cc: Xu Yilun <yilun.xu@linux.intel.com>
> > Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> > Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> > Signed-off-by: Dan Williams <dan.j.williams@intel.com>
> 
> New day, new comments.  Nothing huge, but I would avoid the defining
> an attr group to NULL as that feels like storing up bugs for the future.
> 
> > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> > index d3f16be40102..8b356dd09105 100644
> > --- a/drivers/pci/pci.h
> > +++ b/drivers/pci/pci.h
> > @@ -616,9 +616,12 @@ static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { }
> >  #ifdef CONFIG_PCI_IDE
> >  void pci_ide_init(struct pci_dev *dev);
> >  void pci_ide_init_host_bridge(struct pci_host_bridge *hb);
> > +extern const struct attribute_group pci_ide_attr_group;
> > +#define PCI_IDE_ATTR_GROUP (&pci_ide_attr_group)
> >  #else
> >  static inline void pci_ide_init(struct pci_dev *dev) { }
> >  static inline void pci_ide_init_host_bridge(struct pci_host_bridge *hb) { }
> > +#define PCI_IDE_ATTR_GROUP NULL
> 
> This only works if we assume nothing else ever ends up in pci_host_bridge_groups.
> i.e. it's fragile - think of someone adding something after this.
> Whilst I don't like ifdefs inline, there isn't a better option for this case that
> I can think of.

Fair enough, a comment explaining the hazard is about as ugly as the
ifdef.

[..]
> > +/**
> > + * pci_ide_set_nr_streams() - sets size of the pool of IDE Stream resources
> > + * @hb: host bridge boundary for the stream pool
> > + * @nr: number of streams
> > + *
> > + * Platform PCI init and/or expert test module use only. Limit IDE
> > + * Stream establishment by setting the number of stream resources
> > + * available at the host bridge. Platform init code must set this before
> > + * the first pci_ide_stream_alloc() call if the platform has less than the
> > + * default of 256 streams per host-bridge.
> > + *
> > + * The "PCI_IDE" symbol namespace is required because this is typically
> > + * a detail that is settled in early PCI init. I.e. this export is not
> > + * for endpoint drivers.
> > + */
> > +void pci_ide_set_nr_streams(struct pci_host_bridge *hb, u16 nr)
> > +{
> > +	if (nr > 256)
> > +		nr = 256;
> 
> 
> hb->nr_ide_streams = min(nr, 256);
> maybe

Sure.

 8:  8bcdc030d445 !  8:  37a609df4dd5 PCI/IDE: Report available IDE streams
    @@ drivers/pci/pci.h: static inline void pci_doe_sysfs_teardown(struct pci_dev *pde
      void pci_ide_init(struct pci_dev *dev);
      void pci_ide_init_host_bridge(struct pci_host_bridge *hb);
     +extern const struct attribute_group pci_ide_attr_group;
    -+#define PCI_IDE_ATTR_GROUP (&pci_ide_attr_group)
      #else
      static inline void pci_ide_init(struct pci_dev *dev) { }
      static inline void pci_ide_init_host_bridge(struct pci_host_bridge *hb) { }
    -+#define PCI_IDE_ATTR_GROUP NULL
    - #endif
    - 
    - #ifdef CONFIG_PCI_TSM
     
      ## include/linux/pci-ide.h ##
     @@ include/linux/pci-ide.h: struct pci_ide {
    @@ drivers/pci/ide.c: void pci_ide_init_host_bridge(struct pci_host_bridge *hb)
     + */
     +void pci_ide_set_nr_streams(struct pci_host_bridge *hb, u16 nr)
     +{
    -+	if (nr > 256)
    -+		nr = 256;
    -+	hb->nr_ide_streams = nr;
    ++	hb->nr_ide_streams = min(nr, 256);
     +	WARN_ON_ONCE(!ida_is_empty(&hb->ide_stream_ida));
     +	sysfs_update_group(&hb->dev.kobj, &pci_ide_attr_group);
     +}
    @@ drivers/pci/probe.c: static void pci_release_host_bridge_dev(struct device *dev)
      }
      
     +static const struct attribute_group *pci_host_bridge_groups[] = {
    -+	PCI_IDE_ATTR_GROUP,
    ++#ifdef CONFIG_PCI_IDE
    ++	&pci_ide_attr_group,
    ++#endif
     +	NULL
     +};
     +

  reply	other threads:[~2025-10-30 20:48 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-24  2:04 [PATCH v7 0/9] PCI/TSM: Core infrastructure for PCI device security (TDISP) Dan Williams
2025-10-24  2:04 ` [PATCH v7 1/9] coco/tsm: Introduce a core device for TEE Security Managers Dan Williams
2025-10-29 13:33   ` Jonathan Cameron
2025-10-29 23:47     ` dan.j.williams
2025-10-30  1:00   ` Alexey Kardashevskiy
2025-10-30  9:04   ` Carlos López
2025-10-30 23:16     ` dan.j.williams
2025-10-24  2:04 ` [PATCH v7 2/9] PCI/IDE: Enumerate Selective Stream IDE capabilities Dan Williams
2025-10-29 13:42   ` Jonathan Cameron
2025-10-29 23:55     ` dan.j.williams
2025-10-30  0:59   ` Alexey Kardashevskiy
2025-10-30 21:13     ` dan.j.williams
2025-10-30 21:37     ` Bjorn Helgaas
2025-10-30 23:56       ` Alexey Kardashevskiy
2025-10-31  0:34         ` dan.j.williams
2025-10-31  1:20         ` Bjorn Helgaas
2025-10-30  8:34   ` Aneesh Kumar K.V
2025-10-24  2:04 ` [PATCH v7 3/9] PCI: Introduce pci_walk_bus_reverse(), for_each_pci_dev_reverse() Dan Williams
2025-10-29 14:00   ` Jonathan Cameron
2025-10-29 16:05     ` dan.j.williams
2025-10-30 19:36     ` dan.j.williams
2025-10-24  2:04 ` [PATCH v7 4/9] PCI/TSM: Establish Secure Sessions and Link Encryption Dan Williams
2025-10-26  3:18   ` kernel test robot
2025-10-29 15:53   ` Jonathan Cameron
2025-10-30 19:56     ` dan.j.williams
2025-10-30  1:13   ` Alexey Kardashevskiy
2025-10-30  8:35   ` Aneesh Kumar K.V
2025-10-24  2:04 ` [PATCH v7 5/9] PCI: Add PCIe Device 3 Extended Capability enumeration Dan Williams
2025-10-24  2:04 ` [PATCH v7 6/9] PCI: Establish document for PCI host bridge sysfs attributes Dan Williams
2025-10-29 16:04   ` Jonathan Cameron
2025-10-24  2:04 ` [PATCH v7 7/9] PCI/IDE: Add IDE establishment helpers Dan Williams
2025-10-25 16:53   ` Aneesh Kumar K.V
2025-10-29 18:57     ` dan.j.williams
2025-10-29 16:25   ` Jonathan Cameron
2025-10-24  2:04 ` [PATCH v7 8/9] PCI/IDE: Report available IDE streams Dan Williams
2025-10-29 16:31   ` Jonathan Cameron
2025-10-30 20:48     ` dan.j.williams [this message]
2025-10-24  2:04 ` [PATCH v7 9/9] PCI/TSM: Report active " Dan Williams
2025-10-29 16:34   ` Jonathan Cameron
2025-10-30 21:03     ` dan.j.williams
2025-10-30  2:05   ` Alexey Kardashevskiy
2025-10-27 10:01 ` [PATCH v7 0/9] PCI/TSM: Core infrastructure for PCI device security (TDISP) Aneesh Kumar K.V
2025-10-29  5:20   ` Alexey Kardashevskiy

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