From: <dan.j.williams@intel.com>
To: Terry Bowman <terry.bowman@amd.com>, <dave@stgolabs.net>,
<jonathan.cameron@huawei.com>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <dan.j.williams@intel.com>,
<bhelgaas@google.com>, <shiju.jose@huawei.com>,
<ming.li@zohomail.com>, <Smita.KoralahalliChannabasappa@amd.com>,
<rrichter@amd.com>, <dan.carpenter@linaro.org>,
<PradeepVineshReddy.Kodamati@amd.com>, <lukas@wunner.de>,
<Benjamin.Cheatham@amd.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
<linux-cxl@vger.kernel.org>, <vishal.l.verma@intel.com>,
<alucerop@amd.com>, <ira.weiny@intel.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<terry.bowman@amd.com>
Subject: Re: [PATCH v15 1/9] PCI/AER: Introduce AER-CXL Kfifo in new file, pcie/aer_cxl_vh.c
Date: Tue, 3 Feb 2026 20:25:56 -0800 [thread overview]
Message-ID: <6982ca54e094b_55fa1005@dwillia2-mobl4.notmuch> (raw)
In-Reply-To: <20260203025244.3093805-2-terry.bowman@amd.com>
Terry Bowman wrote:
> CXL virtual hierarchy (VH) RAS handling for CXL Port devices will be added
> soon. This requires a notification mechanism for the AER driver to share
> the AER interrupt with the CXL driver. The notification will be used as an
> indication for the CXL drivers to handle and log the CXL RAS errors.
>
> Note, 'CXL protocol error' terminology will refer to CXL VH and not
> CXL RCH errors unless specifically noted going forward.
>
> Introduce a new file in the AER driver to handle the CXL protocol errors
> named pci/pcie/aer_cxl_vh.c.
>
> Add a kfifo work queue to be used by the AER and CXL drivers. The AER
> driver will be the sole kfifo producer adding work and the cxl_core will be
> the sole kfifo consumer removing work. Add the boilerplate kfifo support.
> Encapsulate the kfifo, RW semaphore, and work pointer in a single structure.
>
> Add CXL work queue handler registration functions in the AER driver. Export
> the functions allowing CXL driver to access. Implement registration
> functions for the CXL driver to assign or clear the work handler function.
> Synchronize accesses using the RW semaphore.
>
> Introduce 'struct cxl_proto_err_work_data' to serve as the kfifo work data.
> This will contain a reference to the PCI error source device and the error
> severity. This will be used when the work is dequeued by the cxl_core driver.
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>
[..]
> diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c
> new file mode 100644
> index 000000000000..de8bca383159
> --- /dev/null
> +++ b/drivers/pci/pcie/aer_cxl_vh.c
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/* Copyright(c) 2025 AMD Corporation. All rights reserved. */
> +
> +#include <linux/types.h>
> +#include <linux/bitfield.h>
> +#include <linux/kfifo.h>
> +#include <linux/aer.h>
> +#include "../pci.h"
> +#include "portdrv.h"
> +
> +#define CXL_ERROR_SOURCES_MAX 128
> +
> +struct cxl_proto_err_kfifo {
> + struct work_struct *work;
> + struct rw_semaphore rw_sema;
> + DECLARE_KFIFO(fifo, struct cxl_proto_err_work_data,
> + CXL_ERROR_SOURCES_MAX);
> +};
> +
> +static struct cxl_proto_err_kfifo cxl_proto_err_kfifo = {
> + .rw_sema = __RWSEM_INITIALIZER(cxl_proto_err_kfifo.rw_sema)
> +};
Minor nit, I have never seen "rw_sema" as an identifier for an
rw_semaphore, would have expected "rwsem". Note I am only commenting on
this because there is something real to fix below.
> +
> +bool is_aer_internal_error(struct aer_err_info *info)
> +{
> + if (info->severity == AER_CORRECTABLE)
> + return info->status & PCI_ERR_COR_INTERNAL;
> +
> + return info->status & PCI_ERR_UNC_INTN;
> +}
> +
> +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info)
> +{
> + if (!info || !info->is_cxl)
> + return false;
> +
> + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_ENDPOINT)
> + return false;
> +
> + return is_aer_internal_error(info);
> +}
> +
> +void cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info)
> +{
> + struct cxl_proto_err_work_data wd = (struct cxl_proto_err_work_data) {
> + .severity = info->severity,
> + .pdev = pdev
> + };
> +
> + guard(rwsem_read)(&cxl_proto_err_kfifo.rw_sema);
> + pci_dev_get(pdev);
If the work item is not registered, nothing will drop this reference.
I would add a comment that the reference is held as long as the pdev is
live in the kfifo.
> + if (!cxl_proto_err_kfifo.work || !kfifo_put(&cxl_proto_err_kfifo.fifo, wd)) {
...while fixing the above, go ahead and wrap this at 80 columns.
> + dev_err_ratelimited(&pdev->dev, "AER-CXL kfifo error");
At this point we know the pdev did not go live in the kfifo so ref can be
dropped here.
> + return;
> + }
> +
> + schedule_work(cxl_proto_err_kfifo.work);
> +}
> +
> +void cxl_register_proto_err_work(struct work_struct *work)
> +{
> + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema);
> + cxl_proto_err_kfifo.work = work;
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_register_proto_err_work, "CXL");
> +
> +void cxl_unregister_proto_err_work(void)
> +{
> + guard(rwsem_write)(&cxl_proto_err_kfifo.rw_sema);
> + cxl_proto_err_kfifo.work = NULL;
I prefer the cancel_work_sync() inside this function rather than
cxl_ras_exit() so the semantic that no invocations spill outside of the
"unregister" barrier.
I realize cxl_cper_unregister_prot_err_work() originally made this a bit
messy so I am ok if a follow-on cleanup fixes up both.
Maybe Dave can fix the above issues up on applying?
With those addressed you can add:
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
next prev parent reply other threads:[~2026-02-04 4:26 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-03 2:52 [PATCH v15 0/9] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-02-03 2:52 ` [PATCH v15 1/9] PCI/AER: Introduce AER-CXL Kfifo in new file, pcie/aer_cxl_vh.c Terry Bowman
2026-02-04 4:25 ` dan.j.williams [this message]
2026-02-03 2:52 ` [PATCH v15 2/9] cxl: Update CXL Endpoint tracing Terry Bowman
2026-02-04 4:29 ` dan.j.williams
2026-02-03 2:52 ` [PATCH v15 3/9] PCI/ERR: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2026-02-03 2:52 ` [PATCH v15 4/9] PCI/AER: Dequeue forwarded CXL error Terry Bowman
2026-02-03 15:26 ` Jonathan Cameron
2026-02-03 17:00 ` Bowman, Terry
2026-02-05 17:13 ` Jonathan Cameron
2026-02-04 4:46 ` dan.j.williams
2026-02-03 2:52 ` [PATCH v15 5/9] PCI: Establish common CXL Port protocol error flow Terry Bowman
2026-02-03 15:40 ` Jonathan Cameron
2026-02-03 18:21 ` Bowman, Terry
2026-02-05 17:16 ` Jonathan Cameron
2026-02-04 5:08 ` dan.j.williams
2026-02-04 17:11 ` Bowman, Terry
2026-02-04 21:22 ` dan.j.williams
2026-02-05 16:07 ` Bowman, Terry
2026-02-05 21:17 ` dan.j.williams
2026-02-03 2:52 ` [PATCH v15 6/9] cxl: Update error handlers to support CXL Port protocol errors Terry Bowman
2026-02-03 15:54 ` Jonathan Cameron
2026-02-03 2:52 ` [PATCH v15 7/9] cxl: Update Endpoint AER uncorrectable handler Terry Bowman
2026-02-03 16:18 ` Jonathan Cameron
2026-02-03 17:31 ` Dave Jiang
2026-02-03 18:35 ` Bowman, Terry
2026-02-03 18:49 ` Dave Jiang
2026-02-03 20:21 ` Dave Jiang
2026-02-03 2:52 ` [PATCH v15 8/9] cxl: Remove Endpoint AER correctable handler Terry Bowman
2026-02-03 16:27 ` Jonathan Cameron
2026-02-03 2:52 ` [PATCH v15 9/9] cxl: Enable CXL protocol error reporting Terry Bowman
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