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Wed, 4 Feb 2026 05:08:58 +0000 From: Date: Tue, 3 Feb 2026 21:08:56 -0800 To: Terry Bowman , , , , , , , , , , , , , , , , , , , CC: , , Message-ID: <6982d468e42eb_55fa1002b@dwillia2-mobl4.notmuch> In-Reply-To: <20260203025244.3093805-6-terry.bowman@amd.com> References: <20260203025244.3093805-1-terry.bowman@amd.com> <20260203025244.3093805-6-terry.bowman@amd.com> Subject: Re: [PATCH v15 5/9] PCI: Establish common CXL Port protocol error flow Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: BYAPR02CA0034.namprd02.prod.outlook.com (2603:10b6:a02:ee::47) To PH8PR11MB8107.namprd11.prod.outlook.com (2603:10b6:510:256::6) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8107:EE_|SJ0PR11MB8269:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a22ff4a-c510-457c-9a21-08de63ab8086 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|1800799024|7053199007|921020; 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Establish a consistent flow for correctable and > uncorrectable CXL protocol errors. > > Provide the solution by adding cxl_port_cor_error_detected() and > cxl_port_error_detected() to handle correctable and uncorrectable handling > through CXL RAS helpers, coordinating uncorrectable recovery in > cxl_do_recovery(), and panicking when the handler returns PCI_ERS_RESULT_PANIC > to preserve fatal cachemem behavior. Gate endpoint handling on the endpoint > driver being bound to avoid processing errors on disabled devices. > > Centralize the RAS base lookup in cxl_get_ras_base(), selecting the > downstream-port dport->regs.ras for Root/Downstream Ports and port->regs.ras > for Upstream Ports/Endpoints. > > Export pcie_clear_device_status() and pci_aer_clear_fatal_status() to enable > cxl_core to clear PCIe/AER state in these flows. > > Signed-off-by: Terry Bowman > Acked-by: Bjorn Helgaas > Reviewed-by: Dave Jiang dave.jiang@intel.com > > --- > > Changes in v14->v15: > - Update commit message and title. Added Bjorn's ack. > - Move CE and UCE handling logic here > > Changes in v13->v14: > - Add Dave Jiang's review-by > - Update commit message & headline (Bjorn) > - Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to > one line (Jonathan) > - Remove cxl_walk_port() (Dan) > - Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is > sufficient (Dan) > - Remove device_lock_if() > - Combined CE and UCE here (Terry) > > Changes in v12->v13: > - Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue > patch (Terry) > - Remove EP case in cxl_get_ras_base(), not used. (Terry) > - Remove check for dport->dport_dev (Dave) > - Remove whitespace (Terry) > > Changes in v11->v12: > - Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and > pci_to_cxl_dev() > - Change cxl_error_detected() -> cxl_cor_error_detected() > - Remove NULL variable assignments > - Replace bus_find_device() with find_cxl_port_by_uport() for upstream > port searches. > > Changes in v10->v11: > - None > --- > drivers/cxl/core/ras.c | 134 +++++++++++++++++++++++++++++++++++++++++ > drivers/pci/pci.c | 1 + > drivers/pci/pci.h | 2 - > drivers/pci/pcie/aer.c | 1 + > include/linux/aer.h | 2 + > include/linux/pci.h | 2 + > 6 files changed, 140 insertions(+), 2 deletions(-) > > diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c > index a6c0bc6d7203..0216dafa6118 100644 > --- a/drivers/cxl/core/ras.c > +++ b/drivers/cxl/core/ras.c > @@ -218,6 +218,68 @@ static struct cxl_port *get_cxl_port(struct pci_dev *pdev) > return NULL; > } > > +static void __iomem *cxl_get_ras_base(struct device *dev) > +{ > + struct pci_dev *pdev = to_pci_dev(dev); > + > + switch (pci_pcie_type(pdev)) { > + case PCI_EXP_TYPE_ROOT_PORT: > + case PCI_EXP_TYPE_DOWNSTREAM: > + { Nit, clang-format puts that { on the same line because coding style says only functions get newlines for open brackets. > + struct cxl_dport *dport; > + struct cxl_port *port __free(put_cxl_port) = find_cxl_port(&pdev->dev, &dport); > + > + if (!dport) { > + pci_err(pdev, "Failed to find the CXL device"); > + return NULL; > + } > + return dport->regs.ras; > + } > + case PCI_EXP_TYPE_UPSTREAM: > + case PCI_EXP_TYPE_ENDPOINT: > + { > + struct cxl_port *port __free(put_cxl_port) = find_cxl_port_by_uport(&pdev->dev); > + > + if (!port) { > + pci_err(pdev, "Failed to find the CXL device"); > + return NULL; > + } > + return port->regs.ras; > + } > + } > + dev_warn_once(dev, "Error: Unsupported device type (%#x)", pci_pcie_type(pdev)); > + return NULL; > +} > + > +static pci_ers_result_t cxl_port_error_detected(struct device *dev); > + > +static void cxl_do_recovery(struct pci_dev *pdev) > +{ > + struct cxl_port *port __free(put_cxl_port) = get_cxl_port(pdev); > + pci_ers_result_t status; > + > + if (!port) { > + pci_err(pdev, "Failed to find the CXL device\n"); > + return; > + } > + > + status = cxl_port_error_detected(&pdev->dev); > + if (status == PCI_ERS_RESULT_PANIC) > + panic("CXL cachemem error."); > + > + /* > + * If we have native control of AER, clear error status in the device > + * that detected the error. If the platform retained control of AER, > + * it is responsible for clearing this status. In that case, the > + * signaling device may not even be visible to the OS. > + */ This comment feels more appropriate as documentation for pcie_aer_is_native(). CXL is just using for the same purpose as all the other callers. You can maybe reference "See pcie_aer_is_native() for expecations on clearing errors", but I otherwise would not expect CXL to carry its own paragraph. > + if (pcie_aer_is_native(pdev)) { > + pcie_clear_device_status(pdev); > + pci_aer_clear_nonfatal_status(pdev); > + pci_aer_clear_fatal_status(pdev); > + } > +} > + > void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base) > { > void __iomem *addr; > @@ -288,6 +350,60 @@ bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base) > return true; > } > > +static void cxl_port_cor_error_detected(struct device *dev) > +{ > + struct pci_dev *pdev = to_pci_dev(dev); > + struct cxl_port *port __free(put_cxl_port) = get_cxl_port(pdev); > + > + if (is_cxl_endpoint(port)) { > + struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); > + struct cxl_dev_state *cxlds = cxlmd->cxlds; > + > + guard(device)(&cxlmd->dev); > + > + if (!dev->driver) { > + dev_warn(&pdev->dev, > + "%s: memdev disabled, abort error handling\n", > + dev_name(dev)); > + return; > + } > + > + if (cxlds->rcd) > + cxl_handle_rdport_errors(cxlds); Isn't this dead code? Only VH topologies will ever get a forwarded CXL error, right? I realize it gets deleted in a future patch, but then why leave dead code in the git history? > + > + cxl_handle_cor_ras(dev, cxlds->serial, cxl_get_ras_base(dev)); > + } else { > + cxl_handle_cor_ras(dev, 0, cxl_get_ras_base(dev)); > + } > +} > + > +static pci_ers_result_t cxl_port_error_detected(struct device *dev) > +{ > + struct pci_dev *pdev = to_pci_dev(dev); > + struct cxl_port *port __free(put_cxl_port) = get_cxl_port(pdev); > + > + if (is_cxl_endpoint(port)) { > + struct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev); > + struct cxl_dev_state *cxlds = cxlmd->cxlds; > + > + guard(device)(&cxlmd->dev); > + > + if (!dev->driver) { > + dev_warn(&pdev->dev, > + "%s: memdev disabled, abort error handling\n", > + dev_name(dev)); > + return PCI_ERS_RESULT_NONE; > + } > + > + if (cxlds->rcd) > + cxl_handle_rdport_errors(cxlds); > + > + return cxl_handle_ras(dev, cxlds->serial, cxl_get_ras_base(dev)); > + } else { > + return cxl_handle_ras(dev, 0, cxl_get_ras_base(dev)); > + } > +} > + > void cxl_cor_error_detected(struct pci_dev *pdev) > { > struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); > @@ -363,6 +479,24 @@ EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); > > static void cxl_handle_proto_error(struct cxl_proto_err_work_data *err_info) > { > + struct pci_dev *pdev = err_info->pdev; > + > + if (err_info->severity == AER_CORRECTABLE) { > + > + if (!pcie_aer_is_native(pdev)) > + return; > + > + if (pdev->aer_cap) > + pci_clear_and_set_config_dword(pdev, > + pdev->aer_cap + PCI_ERR_COR_STATUS, > + 0, PCI_ERR_COR_INTERNAL); > + > + cxl_port_cor_error_detected(&pdev->dev); > + > + pcie_clear_device_status(pdev); > + } else { > + cxl_do_recovery(pdev); > + } > } > > static void cxl_proto_err_work_fn(struct work_struct *work) > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 13dbb405dc31..b7bfefdaf990 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -2248,6 +2248,7 @@ void pcie_clear_device_status(struct pci_dev *dev) > pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta); > pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta); > } > +EXPORT_SYMBOL_GPL(pcie_clear_device_status); No reason to open up this symbol to the world. Only cxl_core.ko needs this exported, and hopefully we never see another bus that abuses PCI like CXL does ever again. [..] > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index 7af10a74da34..4fc9de4c78f8 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -298,6 +298,7 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev) > if (status) > pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_STATUS, status); > } > +EXPORT_SYMBOL_GPL(pci_aer_clear_fatal_status); ditto, too wide of an export.