Re: [PATCH v15 2/9] cxl: Update CXL Endpoint tracing

dan.j.williams
2026-02-04T04:29:27Z

Terry Bowman wrote:
> CXL protocol error handling will be expanded to soon include CXL Port
> support along with existing Endpoint support. 2 updates are needed first:
> - Update calling interfaces to use 'struct device*'
> - Log endpoint serial number
>
> Add serial number parameter to the trace logging. This is used for EPs
> and 0 is provided for CXL port devices without a serial number.
>
> Leave the correctable and uncorrectable trace routines' TP_STRUCT__entry()
> unchanged with respect to member data types and order.
>
> Below is output of correctable and uncorrectable protocol error logging.
> CXL Root Port and CXL Endpoint examples are included below.
>
> The tracing support for CXL Port devices and Endpoints is already implemented.
> Update cxl_handle_ras() & cxl_handle_cor_ras() to also call the CXL trace
> routines.
>
> Root Port:
> cxl_port_aer_correctable_error: device=0000:0c:00.0 host=pci0000:0c serial: 0 status='CRC Threshold Hit'
> cxl_port_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c serial: 0 status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Parity Error'
>
> Endpoint:
> cxl_aer_correctable_error: memdev=mem3 host=0000:0f:00.0 serial=0 status='CRC Threshold Hit'
> cxl_aer_uncorrectable_error: memdev=mem3 host=0000:0f:00.0 serial: 0 status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Parity Error'

Looks good, adding the serial number at the end should preserve
compatibility with libtraceevent parsing of the parameters.

Reviewed-by: Dan Williams <dan.j.williams@intel.com>