From: Dan Williams <dan.j.williams@intel.com>
To: Terry Bowman <terry.bowman@amd.com>, <dave@stgolabs.net>,
<jonathan.cameron@huawei.com>, <dave.jiang@intel.com>,
<alison.schofield@intel.com>, <dan.j.williams@intel.com>,
<bhelgaas@google.com>, <shiju.jose@huawei.com>,
<ming.li@zohomail.com>, <Smita.KoralahalliChannabasappa@amd.com>,
<rrichter@amd.com>, <dan.carpenter@linaro.org>,
<PradeepVineshReddy.Kodamati@amd.com>, <lukas@wunner.de>,
<Benjamin.Cheatham@amd.com>,
<sathyanarayanan.kuppuswamy@linux.intel.com>,
<linux-cxl@vger.kernel.org>, <vishal.l.verma@intel.com>,
<alucerop@amd.com>, <ira.weiny@intel.com>
Cc: <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
<terry.bowman@amd.com>
Subject: Re: [PATCH v16 10/10] cxl: Enable CXL protocol error reporting
Date: Sun, 29 Mar 2026 18:41:12 -0700 [thread overview]
Message-ID: <69c9d4b8e08f1_17890410047@dwillia2-mobl4.notmuch> (raw)
In-Reply-To: <20260302203648.2886956-11-terry.bowman@amd.com>
Terry Bowman wrote:
> CXL protocol errors are not enabled for all CXL devices after boot. These
> must be enabled inorder to process CXL protocol errors.
>
> Introduce cxl_unmask_proto_interrupts() to call pci_aer_unmask_internal_errors().
> pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized.
> But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL
> Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable AER
> correctable internal errors and uncorrectable internal errors for all CXL
> devices.
>
> Signed-off-by: Terry Bowman <terry.bowman@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
>
> ---
> drivers/cxl/core/port.c | 2 ++
> drivers/cxl/core/ras.c | 22 ++++++++++++++++++++++
> drivers/cxl/cxlpci.h | 4 ++++
> 3 files changed, 28 insertions(+)
>
> diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
> index 27271402915f..c33d58fb7264 100644
> --- a/drivers/cxl/core/port.c
> +++ b/drivers/cxl/core/port.c
> @@ -1852,6 +1852,8 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
>
> rc = cxl_add_ep(dport, &cxlmd->dev);
>
> + cxl_unmask_proto_interrupts(cxlmd->cxlds->dev);
> +
Why here? devm_cxl_port_ras_setup() will just redo it, right?
> /*
> * If the endpoint already exists in the port's list,
> * that's ok, it was added on a previous pass.
> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
> index d6112b812c82..bfe6cb35154e 100644
> --- a/drivers/cxl/core/ras.c
> +++ b/drivers/cxl/core/ras.c
> @@ -119,6 +119,24 @@ static void cxl_cper_prot_err_work_fn(struct work_struct *work)
> }
> static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn);
>
> +void cxl_unmask_proto_interrupts(struct device *dev)
> +{
> + if (!dev || !dev_is_pci(dev))
> + return;
> +
> + struct pci_dev *pdev __free(pci_dev_put) = pci_dev_get(to_pci_dev(dev));
Why does this need to hold a reference for a simple to_pci_dev() conversion?
> +
> + if (!pdev->aer_cap) {
> + pdev->aer_cap = pci_find_ext_capability(pdev,
> + PCI_EXT_CAP_ID_ERR);
> + if (!pdev->aer_cap)
> + return;
> + }
> +
> + pci_aer_unmask_internal_errors(pdev);
> +}
> +EXPORT_SYMBOL_NS_GPL(cxl_unmask_proto_interrupts, "CXL");
Why export? The only callers are internal to cxl_core.ko?
---
drivers/cxl/cxlpci.h | 4 ----
drivers/cxl/core/port.c | 2 --
drivers/cxl/core/ras.c | 3 +--
3 files changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index b7cf9d6137b3..184a95e96ea9 100644
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -82,7 +82,6 @@ void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport);
pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
pci_channel_state_t error);
void devm_cxl_port_ras_setup(struct cxl_port *port);
-void cxl_unmask_proto_interrupts(struct device *dev);
#else
static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,
pci_channel_state_t state)
@@ -97,9 +96,6 @@ static inline void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport)
static inline void devm_cxl_port_ras_setup(struct cxl_port *port)
{
}
-static inline void cxl_unmask_proto_interrupts(struct device *dev)
-{
-}
#endif
#endif /* __CXL_PCI_H__ */
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c
index c33d58fb7264..27271402915f 100644
--- a/drivers/cxl/core/port.c
+++ b/drivers/cxl/core/port.c
@@ -1852,8 +1852,6 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)
rc = cxl_add_ep(dport, &cxlmd->dev);
- cxl_unmask_proto_interrupts(cxlmd->cxlds->dev);
-
/*
* If the endpoint already exists in the port's list,
* that's ok, it was added on a previous pass.
diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c
index bfe6cb35154e..1f688110f0f4 100644
--- a/drivers/cxl/core/ras.c
+++ b/drivers/cxl/core/ras.c
@@ -119,7 +119,7 @@ static void cxl_cper_prot_err_work_fn(struct work_struct *work)
}
static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn);
-void cxl_unmask_proto_interrupts(struct device *dev)
+static void cxl_unmask_proto_interrupts(struct device *dev)
{
if (!dev || !dev_is_pci(dev))
return;
@@ -135,7 +135,6 @@ void cxl_unmask_proto_interrupts(struct device *dev)
pci_aer_unmask_internal_errors(pdev);
}
-EXPORT_SYMBOL_NS_GPL(cxl_unmask_proto_interrupts, "CXL");
static void cxl_dport_map_ras(struct cxl_dport *dport)
{
--
2.53.0
next prev parent reply other threads:[~2026-03-30 1:41 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-02 20:36 [PATCH v16 00/10] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-03-02 20:36 ` [PATCH v16 01/10] PCI/AER: Introduce AER-CXL Kfifo Terry Bowman
2026-03-09 12:20 ` Jonathan Cameron
2026-03-28 0:28 ` Dan Williams
2026-03-29 20:33 ` Dan Williams
2026-03-30 15:33 ` Bowman, Terry
2026-03-30 15:15 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 02/10] PCI/CXL: Update unregistration for AER-CXL and CPER-CXL kfifos Terry Bowman
2026-03-09 12:27 ` Jonathan Cameron
2026-03-11 15:03 ` Bowman, Terry
2026-03-09 18:30 ` Dave Jiang
2026-03-29 21:27 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 03/10] cxl: Update CXL Endpoint tracing Terry Bowman
2026-03-29 21:44 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 04/10] PCI/ERR: Introduce PCI_ERS_RESULT_PANIC Terry Bowman
2026-03-29 21:57 ` Dan Williams
2026-03-30 16:40 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 05/10] PCI: Establish common CXL Port protocol error flow Terry Bowman
2026-03-09 12:45 ` [PATCH v16 05/10] PCI: Establish common CXL Port protocol error flowUIRE Jonathan Cameron
2026-03-30 0:08 ` [PATCH v16 05/10] PCI: Establish common CXL Port protocol error flow Dan Williams
2026-03-02 20:36 ` [PATCH v16 06/10] PCI/CXL: Add RCH support to CXL handlers Terry Bowman
2026-03-09 14:00 ` Jonathan Cameron
2026-03-11 15:21 ` Bowman, Terry
2026-03-30 0:31 ` Dan Williams
2026-03-30 17:02 ` Bowman, Terry
2026-03-02 20:36 ` [PATCH v16 07/10] cxl: Update error handlers to support CXL Port devices Terry Bowman
2026-03-09 14:05 ` Jonathan Cameron
2026-03-11 15:37 ` Bowman, Terry
2026-03-12 13:05 ` Jonathan Cameron
2026-03-30 1:07 ` Dan Williams
2026-03-30 16:31 ` Bowman, Terry
2026-03-31 2:11 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 08/10] cxl: Update Endpoint AER uncorrectable handler Terry Bowman
2026-03-09 14:12 ` Jonathan Cameron
2026-03-11 15:58 ` Bowman, Terry
2026-03-30 1:22 ` Dan Williams
2026-03-31 18:52 ` Bowman, Terry
2026-03-31 19:23 ` Dan Williams
2026-03-31 19:52 ` Bowman, Terry
2026-04-02 3:39 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 09/10] cxl: Remove Endpoint AER correctable handler Terry Bowman
2026-03-09 14:13 ` Jonathan Cameron
2026-03-09 18:55 ` Dave Jiang
2026-03-30 1:24 ` Dan Williams
2026-03-02 20:36 ` [PATCH v16 10/10] cxl: Enable CXL protocol error reporting Terry Bowman
2026-03-30 1:41 ` Dan Williams [this message]
2026-03-31 13:31 ` Bowman, Terry
2026-03-31 19:16 ` Dan Williams
2026-03-31 20:50 ` Bowman, Terry
2026-03-31 21:12 ` Bowman, Terry
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