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b=lbEBT3OBSSmAO7DoSAmWi+aWmCIhtRI4mInhT97HzqiRU3V6unIKwXOQdfGBx3E4bRZHEBqJsITWf62ZwRgBlantdfsOuCIdP5tEA00iCZpXiTn2acTOdnKGdN2lHiNOvpoikPWwxI+4bUVQNKg4hIJDF2NdJGu8Ove4pgYvTrw= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DS0PR12MB6390.namprd12.prod.outlook.com (2603:10b6:8:ce::7) by CH3PR12MB7666.namprd12.prod.outlook.com (2603:10b6:610:152::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9094.22; Wed, 10 Sep 2025 18:40:10 +0000 Received: from DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f]) by DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f%5]) with mapi id 15.20.9094.021; Wed, 10 Sep 2025 18:40:09 +0000 Message-ID: <69ef452c-f31d-4955-9a93-5381dbf39ca7@amd.com> Date: Wed, 10 Sep 2025 13:40:05 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v11 15/23] cxl/pci: Map CXL Endpoint Port and CXL Switch Port RAS registers To: Dave Jiang , dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, dan.j.williams@intel.com, bhelgaas@google.com, shiju.jose@huawei.com, ming.li@zohomail.com, Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com, dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com, lukas@wunner.de, Benjamin.Cheatham@amd.com, sathyanarayanan.kuppuswamy@linux.intel.com, linux-cxl@vger.kernel.org, alucerop@amd.com, ira.weiny@intel.com Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20250827013539.903682-1-terry.bowman@amd.com> <20250827013539.903682-16-terry.bowman@amd.com> Content-Language: en-US From: "Bowman, Terry" In-Reply-To: Content-Type: text/plain; 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CXL RPs and DSPs contain RAS registers that require memory >> mapping to enable RAS logging. This initialization is currently missing and >> must be added for CXL RPs and DSPs. >> >> Update cxl_dport_init_ras_reporting() to support RP and DSP RAS mapping. >> Add alongside the existing Restricted CXL Host Downstream Port RAS mapping. >> >> Update cxl_endpoint_port_probe() to invoke cxl_dport_init_ras_reporting(). >> This will initiate the RAS mapping for CXL RPs and DSPs when each CXL EP is >> created and added to the EP port. >> >> Signed-off-by: Terry Bowman >> --- >> Changes in v10->v11: >> - Use local pointer for readability in cxl_switch_port_init_ras() (Jonathan Cameron) >> - Rename port to be ep in cxl_endpoint_port_init_ras() (Dave Jiang) >> - Rename dport to be parent_dport in cxl_endpoint_port_init_ras() >> and cxl_switch_port_init_ras() (Dave Jiang) >> - Port helper changes were in cxl/port.c, now in core/ras.c (Dave Jiang) >> --- >> drivers/cxl/core/core.h | 7 ++++++ >> drivers/cxl/core/ras.c | 47 +++++++++++++++++++++++++++++++++++++++++ >> drivers/cxl/cxl.h | 2 ++ >> drivers/cxl/cxlpci.h | 4 ---- >> drivers/cxl/mem.c | 4 +++- >> drivers/cxl/port.c | 5 +++++ >> 6 files changed, 64 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h >> index 2c81a43d7b05..2fa76a913264 100644 >> --- a/drivers/cxl/core/core.h >> +++ b/drivers/cxl/core/core.h >> @@ -146,6 +146,9 @@ int cxl_port_get_switch_dport_bandwidth(struct cxl_port *port, >> #ifdef CONFIG_CXL_RAS >> int cxl_ras_init(void); >> void cxl_ras_exit(void); >> +void cxl_switch_port_init_ras(struct cxl_port *port); >> +void cxl_endpoint_port_init_ras(struct cxl_port *ep); >> +void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host); >> #else >> static inline int cxl_ras_init(void) >> { >> @@ -155,6 +158,10 @@ static inline int cxl_ras_init(void) >> static inline void cxl_ras_exit(void) >> { >> } >> +static inline void cxl_switch_port_init_ras(struct cxl_port *port) { } >> +static inline void cxl_endpoint_port_init_ras(struct cxl_port *ep) { } >> +static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, >> + struct device *host) { } >> #endif // CONFIG_CXL_RAS >> >> int cxl_gpf_port_setup(struct cxl_dport *dport); >> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c >> index 69559043b772..42b6e0b092d5 100644 >> --- a/drivers/cxl/core/ras.c >> +++ b/drivers/cxl/core/ras.c >> @@ -284,6 +284,53 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host) >> } >> EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); >> >> +static void cxl_uport_init_ras_reporting(struct cxl_port *port, >> + struct device *host) >> +{ >> + struct cxl_register_map *map = &port->reg_map; >> + >> + map->host = host; >> + if (cxl_map_component_regs(map, &port->uport_regs, >> + BIT(CXL_CM_CAP_CAP_ID_RAS))) >> + dev_dbg(&port->dev, "Failed to map RAS capability\n"); >> +} >> + >> +void cxl_switch_port_init_ras(struct cxl_port *port) >> +{ >> + struct cxl_dport *parent_dport = port->parent_dport; >> + >> + if (is_cxl_root(to_cxl_port(port->dev.parent))) >> + return; >> + >> + /* May have parent DSP or RP */ >> + if (parent_dport && dev_is_pci(parent_dport->dport_dev)) { >> + struct pci_dev *pdev = to_pci_dev(parent_dport->dport_dev); >> + >> + if ((pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) || >> + (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM)) >> + cxl_dport_init_ras_reporting(parent_dport, &port->dev); >> + } >> + >> + cxl_uport_init_ras_reporting(port, &port->dev); >> +} >> +EXPORT_SYMBOL_NS_GPL(cxl_switch_port_init_ras, "CXL"); >> + >> +void cxl_endpoint_port_init_ras(struct cxl_port *ep) >> +{ >> + struct cxl_dport *parent_dport; >> + struct cxl_memdev *cxlmd = to_cxl_memdev(ep->uport_dev); >> + struct cxl_port *parent_port __free(put_cxl_port) = >> + cxl_mem_find_port(cxlmd, &parent_dport); >> + >> + if (!parent_dport || !dev_is_pci(parent_dport->dport_dev)) { >> + dev_err(&ep->dev, "CXL port topology not found\n"); >> + return; >> + } >> + >> + cxl_dport_init_ras_reporting(parent_dport, cxlmd->cxlds->dev); >> +} >> +EXPORT_SYMBOL_NS_GPL(cxl_endpoint_port_init_ras, "CXL"); >> + >> static void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base) >> { >> void __iomem *addr; >> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h >> index 8f6224ac6785..32fccad9a7f6 100644 >> --- a/drivers/cxl/cxl.h >> +++ b/drivers/cxl/cxl.h >> @@ -586,6 +586,7 @@ struct cxl_dax_region { >> * @parent_dport: dport that points to this port in the parent >> * @decoder_ida: allocator for decoder ids >> * @reg_map: component and ras register mapping parameters >> + * @uport_regs: mapped component registers >> * @nr_dports: number of entries in @dports >> * @hdm_end: track last allocated HDM decoder instance for allocation ordering >> * @commit_end: cursor to track highest committed decoder for commit ordering >> @@ -606,6 +607,7 @@ struct cxl_port { >> struct cxl_dport *parent_dport; >> struct ida decoder_ida; >> struct cxl_register_map reg_map; >> + struct cxl_component_regs uport_regs; >> int nr_dports; >> int hdm_end; >> int commit_end; >> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h >> index ad24d81e9eaa..a6da0abfa506 100644 >> --- a/drivers/cxl/cxlpci.h >> +++ b/drivers/cxl/cxlpci.h >> @@ -84,7 +84,6 @@ void read_cdat_data(struct cxl_port *port); >> void cxl_cor_error_detected(struct pci_dev *pdev); >> pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, >> pci_channel_state_t state); >> -void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host); >> #else >> static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } >> >> @@ -93,9 +92,6 @@ static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, >> { >> return PCI_ERS_RESULT_NONE; >> } >> - >> -static inline void cxl_dport_init_ras_reporting(struct cxl_dport *dport, >> - struct device *host) { } >> #endif >> >> #endif /* __CXL_PCI_H__ */ >> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c >> index 6e6777b7bafb..f7dc0ba8905d 100644 >> --- a/drivers/cxl/mem.c >> +++ b/drivers/cxl/mem.c >> @@ -7,6 +7,7 @@ >> >> #include "cxlmem.h" >> #include "cxlpci.h" >> +#include "core/core.h" >> >> /** >> * DOC: cxl mem >> @@ -166,7 +167,8 @@ static int cxl_mem_probe(struct device *dev) >> else >> endpoint_parent = &parent_port->dev; >> >> - cxl_dport_init_ras_reporting(dport, dev); >> + if (dport->rch) >> + cxl_dport_init_ras_reporting(dport, dev); > So the endpoint port probe calls this via cxl_endpoint_port_init_ras(), and if it's RCH the memedev probe also calls this. Trying to understand why it happens for both drivers for the RCH case... This is legacy and I was trying to leave it intact without changes unless  necessary. But, it can be cleaned-up. I can remove here and will leave the  call from  endpoint creation in port.c for RCH and VH. I will add an RCH  check used in discovering the RCD endpoint parent correctly. Thanks for  pointing out. Terry