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[87.20.3.207]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-499899afae3sm98004825e9.3.2026.08.15.04.04.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Aug 2026 04:04:49 -0700 (PDT) Message-ID: <6a8047d1.3527643f.2d620e.3236@mx.google.com> X-Google-Original-Message-ID: Date: Sat, 15 Aug 2026 13:04:45 +0200 From: Christian Marangi To: Manivannan Sadhasivam Cc: Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 2/2] PCI: mediatek-gen3: Add 2-lanes mode support for Airoha AN7581 References: <20260806165334.7328-3-ansuelsmth@gmail.com> <20260813170820.GA1143871@bhelgaas> <6a7e1b73.e11288f4.1351ae.5625@mx.google.com> <5qulrgfnwzuo556hxsyg3iweqv6i57ll3chhhb3nxe7lgr6fff@4l3s5rotnpab> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5qulrgfnwzuo556hxsyg3iweqv6i57ll3chhhb3nxe7lgr6fff@4l3s5rotnpab> On Sat, Aug 15, 2026 at 08:16:56AM +0200, Manivannan Sadhasivam wrote: > On Thu, Aug 13, 2026 at 09:30:54PM +0200, Christian Marangi wrote: > > On Thu, Aug 13, 2026 at 12:08:20PM -0500, Bjorn Helgaas wrote: > > > On Thu, Aug 06, 2026 at 06:53:32PM +0200, Christian Marangi wrote: > > > > The Airoha AN7581 SoC supports configuring the first PCIe0 lane to 2-lanes > > > > mode (x2 link) by bonding it with the second PCIe lane (PCIe1). This is > > > > done by configuring the PCIe MUX in the SCU register. > > > > > > > > To correctly configure PCIe0 in x2 link, define in DT the following > > > > additional properties: > > > > > > > > - additional reg, 'sec-pcie-mac' for the secondary PCIe. > > > > - PERSTOUT reset for both main and secondary PCIE0, called 'perstout' and > > > > 'sec-perstout' > > > > - 'airoha,scu' property to correctly configure the SCU register for the > > > > PCIe MUX > > > > - 'num-lanes' set to '2' to enable PCIe0 in x2 link > > > > > > > > In such configuration the EQ preset are configured to the same values. > > > > > > > > To permit correct configuration of the PCIe link, additional logic is added > > > > to assert and deassert the PERSTOUT resets. Support of these additional > > > > reset was introduced in Airoha clk driver with commit > > > > 6712f48eb3a1 ("clk: en7523: add support for dedicated PCIe PERSTOUT reset") > > > > and on backporting of this commit also the clk driver change will be > > > > needed. > > > > > > I don't see 6712f48eb3a1 in upstream or linux-next. Is this SHA1 > > > going to valid if we merge this for v7.3? > > > > I picked that sha1 from the git pull for the staging clk tree. > > > > Ah, I missed it. In this case the SHA should be dropped and maybe we can refer > the lore link of the patch? > Just yesterday it was picked and it's present in clk-next [1]. The commit didn't change as merge commit are used so the sha1 is valid. I think we can keep it? [1] https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/commit/drivers/clk/clk-en7523.c?h=clk-next&id=6712f48eb3a15842925171441505fa2e7699c57e -- Ansuel